[ { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-agent-docs", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; 'AI-generated insights from data inside the product' is a software/application-layer capability, not something a processor itself delivers. The evidence only covers performance, overclocking, and benchmarks, confirming this axis is a category error for a CPU.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product; autonomous background automation orchestration is an application/software-platform axis, not something a processor itself provides—wrong axis for this product category.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware; delegating tasks to a built-in AI assistant is a software/product-feature axis that doesn't apply to a processor itself. The 'Ryzen AI Software' mention is developer tooling for building AI apps, not a built-in assistant users delegate tasks to.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-headless", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware and has no software agent/MCP client role; plugging MCP servers into tools is a category error for a processor product.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; connecting an agent via an official MCP server is a software/service integration concern entirely outside the category of a processor's capabilities.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-nl-commands", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-official-cli", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware, not a software product with an agent-facing CLI; official CLI/agentic tooling is a category error for this product type.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-public-api", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product; issuing scoped API credentials for an agent is a software/identity-management concern entirely outside a processor's product category.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-sdks", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware with no service/event layer; webhooks/subscriptions are a software-integration axis that doesn't apply to a physical processor.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "api-interactive-docs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a physical CPU product; interactive API references with runnable examples are a software/developer-portal concept and not applicable to a hardware product category.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "api-machine-spec", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU product has no API surface to document via OpenAPI-style specs; this axis applies to software services/platforms, not physical hardware like a processor.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; sandboxed environments for testing vs. production data is a software/platform agentic-workflow concern, not something a processor SKU ships or documents.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "api-versioning-policy", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns software API versioning and deprecation policy, which applies to SaaS/developer platforms, not a physical CPU product; a hardware component has no API surface of this kind for end users.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns AI-native bulk operations across items (an application/software automation capability), which is a category error for a CPU hardware product; the CPU itself does not perform such operations.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns event-driven automation/rule engines, which is a software/platform capability, not applicable to a physical CPU product.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Scheduling recurring jobs/workflows is a software/automation-platform capability, not something a CPU hardware product provides; this axis is a category error for a processor.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns versioning, reviewing, and rolling back software automations, which is a software/workflow-tool concept entirely outside the scope of a physical CPU product like the Ryzen 9 9950X3D.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "developer-toolchain-maturity", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Evidence shows official OS compatibility listings (RHEL, Ubuntu) and community-confirmed AVX-512 support, suggesting baseline OS/tooling recognition, but there is no evidence of AMD-specific compiler optimization guides, toolchain documentation, or first-class developer tooling status. Missing for 10: official compiler/optimization guidance (GCC/LLVM tuning docs), developer-targeted architecture manuals, and independent confirmation of tooling maturity beyond basic OS support.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-14", "amd-ryzen-9-9950x3d-comm-1", "amd-ryzen-9-9950x3d-comm-3" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "expansion-io", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "AMD's docs confirm PCIe 5.0 storage support, NVMe RAID/boot configurations, and ECC memory support (with motherboard dependency), giving some concrete I/O planning data. However, missing for 10: exact PCIe lane count/allocation, USB/Thunderbolt external connectivity specs, and dock-compatible port bandwidth details that a developer would need for a full build-planning picture.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-13", "amd-ryzen-9-9950x3d-docs-8", "amd-ryzen-9-9950x3d-docs-7" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "high-fps-gaming", "verdict": "full", "quality": 9, "confidence": "high", "rationale": "Vendor claims of massive 3D V-Cache (up to 208MB) driving 'ultimate gaming performance' are corroborated by independent benchmarks showing the 9950X3D is the fastest 16-core gaming chip, beats Intel's 285K by 37% and 14900K by 26%, and nearly matches the dedicated gaming champion 9800X3D, with community discussion confirming real-world benefits from the cache. Missing for 10: no integrated GPU gaming benchmarks or iGPU class comparison since this is a desktop chip without significant iGPU gaming evidence.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-6", "amd-ryzen-9-9950x3d-docs-12", "amd-ryzen-9-9950x3d-comm-1", "amd-ryzen-9-9950x3d-comm-2", "amd-ryzen-9-9950x3d-comm-3", "amd-ryzen-9-9950x3d-comm-4" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "local-llm-runtime-support", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence only shows a generic marketing link to 'Ryzen AI Software For Developers' with no indication it applies to the 9950X3D desktop CPU (which lacks an NPU) and no mention of llama.cpp, MLX, ONNX Runtime, or any concrete runtime documentation naming this chip. Linux OS support (RHEL/Ubuntu) is noted but that's generic OS compatibility, not local-AI runtime support documentation.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-5", "amd-ryzen-9-9950x3d-docs-14" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "media-engine-encode", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "memory-spec-bandwidth", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains no published memory type (e.g., DDR5 speed), no memory capacity ceiling, and no bandwidth figures or clock/channel specs from which bandwidth could be derived — only marketing mentions of EXPO overclocking, ECC 'requires mobo support', and on-die 3D V-Cache (which is not system RAM). Missing for 10: memory type/speed spec, max supported memory capacity, number of channels, and bandwidth or derivable throughput numbers.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-2", "amd-ryzen-9-9950x3d-docs-7", "amd-ryzen-9-9950x3d-docs-12" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "multicore-build-performance", "verdict": "partial", "quality": 7, "confidence": "medium", "rationale": "AMD docs confirm core/thread count (up to 32 threads) and boost tuning via PBO/Ryzen Master, and independent reviews (TechPowerup, Tom's Hardware) corroborate strong productivity performance alongside class-leading gaming benchmarks. However, evidence lacks explicit compile-time or multi-threaded workload benchmarks (e.g., Cinebench multi-core, code build times) to directly validate 'compile big codebases' claims. Missing for 10: explicit multi-core/compile benchmark numbers, detailed core/thread topology breakdown, independent parallel-workload testing beyond general productivity mentions.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-13", "amd-ryzen-9-9950x3d-docs-1", "amd-ryzen-9-9950x3d-comm-1", "amd-ryzen-9-9950x3d-comm-3" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "npu-developer-access", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence only shows generic marketing links to 'Ryzen AI Software For Developers' but never states that the 9950X3D itself contains an NPU, nor gives any TOPS figure or precision spec, nor confirms an SDK/runtime ships for this specific chip (Ryzen AI is typically a mobile-chip NPU feature). Missing for 10: NPU presence confirmation on this SKU, a published TOPS figure with precision, and evidence of a shipping SDK/runtime tied to this desktop chip.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-5" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A physical CPU has no API/UI dichotomy relevant to AI-native automation; this story applies to software/services, not to a hardware processor product.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware, not a data-hosting or SaaS platform; there is no user data stored 'in' the product to export, so data portability/export in open formats is a category error for this product type.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "openness-open-license", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A physical CPU is hardware, not source-available software; 'reading source under an open license' is a category error for this product type.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story asks about self-hosting a software product, which is a category error for a physical CPU — the axis simply doesn't apply to a hardware component.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A desktop CPU is hardware with no data storage/hosting service; data residency/region selection is a cloud/SaaS concept that doesn't apply to a processor.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "privacy-no-training", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; controlling whether data is used to train AI models is a data-governance/policy axis belonging to software/cloud services, not a physical processor. No evidence pack content addresses this, and the axis is a category error for a CPU.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU hardware product has no data-retention/deletion controls to expose; this is a software/platform privacy axis, not applicable to a processor.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; telemetry/usage-tracking opt-out is a software/service axis that does not apply to a physical processor.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "published-spec-sheet", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack is dominated by marketing language ('personalize performance', 'colossal 208MB', 'accelerate every step') rather than a transparent spec sheet; while a few technical bullets exist (ECC support, NVMe RAID modes, supported OSes), there is no evidence of published clock speeds, TDP/power figures, memory speed/type support, or AI TOPS numbers with stated test conditions.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-7", "amd-ryzen-9-9950x3d-docs-8", "amd-ryzen-9-9950x3d-docs-14", "amd-ryzen-9-9950x3d-docs-6", "amd-ryzen-9-9950x3d-docs-12" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "run-70b-local-llm", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains no data on memory bandwidth, maximum supported RAM capacity, or any benchmarks/claims about running large (70B-class) LLMs locally; it focuses on gaming, overclocking, and 3D V-Cache for gaming/productivity workloads. Missing for 10: published memory bandwidth figures, max RAM/channel config data, and any LLM inference benchmarks or vendor guidance for local AI workloads.", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "single-thread-responsiveness", "verdict": "full", "quality": 9, "confidence": "high", "rationale": "Independent benchmarks (TechPowerUp, Tom's Hardware) confirm the 9950X3D delivers leading real-world single-thread-sensitive performance (gaming, near-parity with 9800X3D, beating Intel chips by 26-37%), and community commentary corroborates responsiveness gains beyond marketing claims. Missing for 10: dedicated single-thread-only benchmark isolation (e.g. Cinebench single-core scores) rather than aggregate gaming/productivity figures.", "evidenceIds": [ "amd-ryzen-9-9950x3d-comm-1", "amd-ryzen-9-9950x3d-comm-2", "amd-ryzen-9-9950x3d-comm-3", "amd-ryzen-9-9950x3d-comm-4" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "socket-upgrade-path", "verdict": "full", "quality": 8, "confidence": "medium", "rationale": "AMD explicitly documents a multi-year socket support commitment ('AMD is the only processor manufacturer committed to multi-year socket support... start with what fits your build today and upgrade to next-gen performance tomorrow'), directly matching the platform-upgrade story. Missing for 10: independent/community confirmation of actual multi-generation compatibility (e.g. AM5 supporting multiple CPU generations in practice) and specifics on how many generations/years are guaranteed.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-11", "amd-ryzen-9-9950x3d-docs-4" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "sustained-perf-per-watt", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "AMD's marketing highlights creator workloads (DaVinci Resolve, 3D rendering) and tunable power via PBO, and independent reviews broadly call the chip 'energy efficient' with 'strong productivity performance,' but none of the evidence gives documented power envelope specs or dedicated long-render/export sustained perf-per-watt testing. missing for 10: explicit TDP/power envelope documentation, independent sustained-load (render/export) thermal-throttle or perf-per-watt benchmarks.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-1", "amd-ryzen-9-9950x3d-docs-9", "amd-ryzen-9-9950x3d-comm-1", "amd-ryzen-9-9950x3d-comm-3" ] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "thin-quiet-battery", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-9-9950x3d", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "low", "rationale": "Evidence pack shows OS support listing (RHEL, Ubuntu) but no documentation or hands-on evidence about virtualization features (SVM/AMD-V, IOMMU), hypervisor compatibility (KVM, VMware, Hyper-V), or Docker/container workflows on this CPU. missing for 10: virtualization extension docs, hypervisor compatibility evidence, container/Docker workflow evidence, developer hands-on reports.", "evidenceIds": [ "amd-ryzen-9-9950x3d-docs-14" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-agent-docs", "verdict": "full", "quality": 7, "confidence": "medium", "rationale": "A direct probe confirms that AMD's Ryzen AI developer docs serve a working llms.txt file (HTTP 200 with structured content) at ryzenai.docs.amd.com, which an AI agent could be pointed at directly. Missing for 10: broader agent-oriented documentation structure beyond the single llms.txt file, and independent/community confirmation of agents actually using it.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-probe-1", "amd-ryzen-ai-max-plus-395-probe-rt-1" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "AMD Ryzen AI Max+ 395 is a hardware processor/SDK platform for running AI models, not an end-user application that holds 'my data' and surfaces insights from it; this story targets data-centric SaaS/app products, so the axis is a category mismatch for a chip/SDK.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/APU product, not an automation/orchestration platform; setting up autonomous background automations is a software/agent-platform axis that doesn't apply to a chip.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "AMD Ryzen AI Max+ 395 is a hardware processor/SoC with an AI development SDK for building and running models; it is not a product with a built-in end-user AI assistant to delegate tasks to. This axis applies to consumer assistant products/agents, not to a CPU/NPU platform whose evidence only covers developer tooling like ONNX Runtime, Quark quantization, and Lemonade SDK.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-headless", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "The Ryzen AI software stack supports headless Linux server OSes (Ubuntu, RHEL) and exposes CLI/API-driven inference via ONNX Runtime (C++/Python APIs) and the Lemonade SDK for llama.cpp/OGA, which are automatable without a GUI. However, there is no explicit documentation of CI pipelines, containerized/Docker deployment, or automated build/test workflows for this hardware. Missing for 10: explicit CI/automation examples, containerization support, and independent confirmation of headless scripted runs.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-3", "amd-ryzen-ai-max-plus-395-docs-4", "amd-ryzen-ai-max-plus-395-docs-8" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/APU product, not an agent or platform with an MCP client/server role; plugging MCP servers into a chip is a category error.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "AMD Ryzen AI Max+ 395 is a hardware CPU/APU product, not an agent or service that would expose an MCP server; this axis is a category error for a processor.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-nl-commands", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-official-cli", "verdict": "none", "quality": 0, "confidence": "low", "rationale": "Evidence describes SDKs (ONNX Runtime, Quark, Lemonade SDK) and APIs but never mentions an official command-line interface for Ryzen AI Max+ 395 developers; no CLI tool, install command, or CLI documentation is cited.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-public-api", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "AMD documents software-level APIs (ONNX Runtime C++/Python APIs, Vitis AI EP, Lemonade SDK) for driving AI workloads on the NPU, but there is no public REST/OpenAPI-style programmatic interface for 'driving the product' as an agentic system — probes for OpenAPI/swagger specs all 404. missing for 10: a documented public REST/agent-facing API or SDK entry point beyond ML framework runtimes, independent confirmation of API usage for agentic control.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-3", "amd-ryzen-ai-max-plus-395-docs-4", "amd-ryzen-ai-max-plus-395-probe-3" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/SoC product, not an API service or IAM system; issuing scoped API credentials for agents is a category error for this product type.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-sdks", "verdict": "full", "quality": 7, "confidence": "medium", "rationale": "AMD provides official Ryzen AI SDK docs covering ONNX Runtime with C++/Python APIs, the Vitis AI EP, AMD Quark quantization toolkit, and the Lemonade SDK for LLMs, all live and crawlable at ryzenai.docs.amd.com, giving AI-native developers concrete official SDKs to build against. Missing for 10: independent hands-on developer reports validating SDK usability/completeness, and no OpenAPI/formal API reference confirmed (probe found 404s for openapi endpoints).", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-1", "amd-ryzen-ai-max-plus-395-docs-2", "amd-ryzen-ai-max-plus-395-docs-3", "amd-ryzen-ai-max-plus-395-docs-4", "amd-ryzen-ai-max-plus-395-probe-1", "amd-ryzen-ai-max-plus-395-probe-rt-1" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/APU product; webhooks/event subscriptions are a software/service integration concern that does not apply to a silicon chip's own capabilities.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "api-interactive-docs", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence shows static documentation pages (docs-1 through docs-4) and probes explicitly confirming no OpenAPI/swagger spec and no interactive API reference (probe-3 shows 404s for all candidate OpenAPI paths). There is no evidence of runnable examples or an interactive API explorer anywhere in the pack.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-probe-3", "amd-ryzen-ai-max-plus-395-probe-2", "amd-ryzen-ai-max-plus-395-docs-3" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "api-machine-spec", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "AMD's Ryzen AI docs describe C++/Python SDK APIs (ONNX Runtime, Vitis AI EP) but no machine-readable OpenAPI/Swagger spec was found; explicit probes to /openapi.json, /swagger.json, and similar paths all returned 404.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-probe-3", "amd-ryzen-ai-max-plus-395-docs-3" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns sandboxed testing environments isolated from production data — a software/platform deployment concept that doesn't apply to a hardware CPU/APU product line like this one.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "api-versioning-policy", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "Evidence shows the Ryzen AI software stack exposes C++/Python APIs via ONNX Runtime and mentions SDKs like Quark and Lemonade, but nothing documents API versioning practices or a deprecation policy for these interfaces. Missing for 10: any versioning scheme, changelog, or explicit deprecation/EOL policy for the Ryzen AI APIs.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-3", "amd-ryzen-ai-max-plus-395-docs-4", "amd-ryzen-ai-max-plus-395-probe-3" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/APU product; 'bulk operations across many items' is a software/application-level automation feature not applicable to a silicon chip's product story.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/SoC product; rule-based automation triggers on events is an application/software-platform feature, not something a processor exposes. The story is a category error for this product type.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/APU product, not a workflow/job orchestration platform; scheduling recurring jobs is a software/OS-level concern outside this product's category.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/SoC product; versioning, reviewing, and rolling back 'automations' is a software/workflow-tool concept that does not apply to a chip's category.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "developer-toolchain-maturity", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "AMD provides official Ryzen AI docs, ONNX Runtime + Vitis AI EP, the Quark quantization toolkit, and the Lemonade SDK, plus OS support for Windows 11, RHEL, and Ubuntu, indicating a real first-party tooling stack. However, community reports show developers relying on third-party runtimes (llama.cpp/Vulkan, Ollama) rather than a mature native compiler/optimization path, and cite memory-bandwidth bottlenecks and confusing benchmarks/naming as friction points, suggesting the ecosystem is still maturing rather than unambiguously tier-one. Missing for 10: evidence of mature first-party compiler toolchains, independent benchmarks confirming optimization guidance efficacy, and confirmation that NPU/GPU stack is treated as tier-one by major ML frameworks beyond ONNX.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-1", "amd-ryzen-ai-max-plus-395-docs-2", "amd-ryzen-ai-max-plus-395-docs-4", "amd-ryzen-ai-max-plus-395-docs-8", "amd-ryzen-ai-max-plus-395-comm-6", "amd-ryzen-ai-max-plus-395-comm-7", "amd-ryzen-ai-max-plus-395-comm-8" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "expansion-io", "verdict": "partial", "quality": 2, "confidence": "low", "rationale": "AMD's product page lists some I/O-adjacent specs (NVMe boot/RAID support, max 4 displays, OS support) but there is no documented PCIe generation or lane count, and no external connectivity specs (USB/Thunderbolt/dock) to plan a build around. missing for 10: PCIe generation, PCIe lane count, USB/Thunderbolt/external port specs, dock compatibility documentation.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-7", "amd-ryzen-ai-max-plus-395-docs-9", "amd-ryzen-ai-max-plus-395-docs-8" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "high-fps-gaming", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains no vendor gaming claims (cache/boost/iGPU class positioning) and no independent game benchmark data or FPS figures; community comments are about AI/LLM token throughput and general benchmark methodology complaints, not real-game performance.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-comm-2", "amd-ryzen-ai-max-plus-395-comm-3" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "local-llm-runtime-support", "verdict": "full", "quality": 8, "confidence": "high", "rationale": "AMD's own Ryzen AI docs confirm ONNX Runtime with Vitis AI Execution Provider support, and explicitly mention the Lemonade SDK enabling llama.cpp on this platform; community hands-on reports independently confirm llama.cpp (Vulkan) and Ollama running well on Strix Halo silicon. missing for 10: explicit MLX support (Apple-specific, not applicable here but leaves a gap in the story's named runtimes), and clearer first-party NPU-specific runtime benchmarks beyond GPU/CPU token-rate anecdotes.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-1", "amd-ryzen-ai-max-plus-395-docs-3", "amd-ryzen-ai-max-plus-395-docs-4", "amd-ryzen-ai-max-plus-395-comm-6", "amd-ryzen-ai-max-plus-395-comm-7" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "media-engine-encode", "verdict": "none", "quality": 0, "confidence": "low", "rationale": "Evidence pack contains no documentation of hardware media/video encode-decode engines (AV1, HEVC, ProRes-class) on this chip; all citations focus on AI/NPU software stack, CPU/GPU specs, TDP, and community discussion of LLM performance. Missing for 10: any mention of media/video codec engine, encode/decode capability, or streaming/editing hardware acceleration documentation.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "memory-spec-bandwidth", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack includes AMD's spec page items but none cite memory type, capacity ceiling, or bandwidth figures (only TDP, NVMe, OS, and display specs are shown); community posts discuss bandwidth being a bottleneck qualitatively but no vendor numbers are cited to let a developer size workloads.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-5", "amd-ryzen-ai-max-plus-395-docs-9", "amd-ryzen-ai-max-plus-395-comm-6", "amd-ryzen-ai-max-plus-395-comm-8" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "multicore-build-performance", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "No evidence pack item documents core counts, boost clock behavior, or independent multi-core/compile benchmarks; the AMD docs and product page instead focus on AI/NPU software stack, TDP, and I/O specs. Community comments (comm-2) even push back on judging this chip by CPU-only benchmarks, but no concrete multi-core compile benchmark or core/boost spec is cited either way.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "npu-developer-access", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Strong evidence of an official, shipping SDK/runtime stack (Ryzen AI Software docs, ONNX Runtime + Vitis AI Execution Provider, AMD Quark quantization toolkit, Lemonade SDK for LLMs) confirming real developer-facing NPU acceleration tooling. However, the evidence pack contains no published TOPS figure or precision spec for the NPU itself, which the story explicitly requires. Missing for 10: a documented TOPS number with precision (e.g., INT8/INT4) for the XDNA2 NPU, and independent benchmark corroboration of that figure.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-1", "amd-ryzen-ai-max-plus-395-docs-2", "amd-ryzen-ai-max-plus-395-docs-3", "amd-ryzen-ai-max-plus-395-docs-4", "amd-ryzen-ai-max-plus-395-probe-rt-1" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware processor product, not a UI/application with an API vs UI parity question — there is no 'UI' for a CPU to compare against an API. The axis is a category error for a hardware SKU.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "AMD Ryzen AI Max+ 395 is a hardware processor/chip, not a data-holding service or platform where a user stores personal data that could be exported; the 'export data and leave' story is a category error for this product type.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "openness-open-license", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The product is a proprietary AMD CPU/APU design; while some accompanying SDKs (Lemonade, ONNX EP) are noted as open-source, there is no evidence that the chip's own source/design (microarchitecture, RTL, etc.) is available under any open license. The axis is fair to ask (some hardware vendors do open designs) but no evidence supports it here.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-4" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The Ryzen AI Max+ 395 is a physical CPU/APU, not a software service or platform with a hosted vs. self-hosted deployment choice — 'self-hosting the core product' is a category error for silicon hardware, which is inherently run on the owner's own machine by nature rather than as a deployment option.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "AMD Ryzen AI Max+ 395 is a hardware CPU/APU chip; data residency/region storage is a cloud-service/SaaS concept and does not apply to a local processor product.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "privacy-no-training", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence describes local on-device AI inference (NPU, ONNX Runtime, local LLM execution via llama.cpp/Ollama) but contains no explicit statement about data-training opt-outs or privacy guarantees regarding model training; while local processing implies data doesn't leave the device, no documentation or claim addresses this story directly.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chip (CPU/APU), not a data-hosting service or SaaS product; data retention and deletion controls are not applicable to a physical processor — inference runs locally on-device and there is no vendor-hosted data lifecycle to manage.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU/APU product; telemetry opt-out is a software/service privacy axis that doesn't apply to a physical processor SKU itself.", "evidenceIds": [] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "published-spec-sheet", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "AMD's product page does publish concrete spec-sheet items (cTDP 45-120W, NVMe RAID support, OS support, display counts, voltage offset support) rather than pure marketing prose, and the Ryzen AI docs give technical detail on the software stack. However, the pack contains no explicit clock-speed figures or AI TOPS number with stated test conditions, and community commentary explicitly complains that AMD's benchmark comparisons are misleading/incomplete rather than rigorously documented. missing for 10: published boost/base clock figures, an explicit AI TOPS figure with test-methodology footnotes, and independent verification that the spec sheet's numbers hold up under real-world testing.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-5", "amd-ryzen-ai-max-plus-395-docs-6", "amd-ryzen-ai-max-plus-395-docs-7", "amd-ryzen-ai-max-plus-395-docs-8", "amd-ryzen-ai-max-plus-395-docs-9", "amd-ryzen-ai-max-plus-395-comm-2", "amd-ryzen-ai-max-plus-395-comm-3" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "run-70b-local-llm", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Community hands-on reports confirm the platform (128GB unified memory) can actually run large quantized models like Qwen3.5-122B-A10B at Q4 and similar 35B+ models via llama.cpp, showing real-world feasibility of 70B-class local inference. However, users consistently note memory bandwidth is the limiting factor for tokens/sec, and no official AMD-published memory bandwidth spec appears in the evidence pack. Missing for 10: an official AMD-published memory bandwidth figure, first-party benchmarks for 70B-class models, and confirmation that performance is 'practical' (not just possible) at long context lengths.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-comm-6", "amd-ryzen-ai-max-plus-395-comm-7", "amd-ryzen-ai-max-plus-395-comm-8" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "single-thread-responsiveness", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "No independent single-thread CPU benchmark data appears anywhere in the evidence pack; the only performance-related community comments concern GPU/LLM token throughput and memory bandwidth, and one explicitly notes the CPU is not the reason to choose this part ('If you're just going to use the CPU obviously the 395 is not what you want'). There's no vendor or third-party single-thread benchmark citation to support the story.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-comm-2", "amd-ryzen-ai-max-plus-395-comm-6", "amd-ryzen-ai-max-plus-395-comm-8" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "socket-upgrade-path", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains no mention of a socket, upgrade path, or multi-generation platform commitment for the Ryzen AI Max+ 395; all specs shown are TDP, display, storage, and OS support with no socket/upgrade language. Community citations also reference it in fixed-configuration devices (e.g., Framework Desktop, mini-PCs) rather than a socketed upgrade path. missing for 10: any documented socket name, generational upgrade commitment, or evidence of user-replaceable CPU in a motherboard.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-5", "amd-ryzen-ai-max-plus-395-docs-9", "amd-ryzen-ai-max-plus-395-comm-6" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "sustained-perf-per-watt", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "AMD documents a configurable TDP range (45-120W) for the chip, but there is no independent benchmark or hands-on testing demonstrating sustained performance-per-watt or absence of thermal throttling during long renders/exports; community comments focus on LLM token throughput and even note frustration that AMD hasn't addressed power usage. missing for 10: independent sustained-load/thermal throttling benchmarks, creator-workload (render/export) power efficiency data, cooling/chassis-specific real-world tests.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-5", "amd-ryzen-ai-max-plus-395-comm-5", "amd-ryzen-ai-max-plus-395-comm-2" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "thin-quiet-battery", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack shows a configurable TDP range of 45–120W and OS/platform specs, but contains no mention of fanless designs, thin-and-light chassis, or battery-life benchmarks; a community comment even complains AMD hasn't focused on reducing power usage. This is a fair axis for a laptop-class chip, but no supporting evidence exists.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-5", "amd-ryzen-ai-max-plus-395-comm-5" ] }, { "productId": "amd-ryzen-ai-max-plus-395", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack lists supported OSes (Windows 11, RHEL, Ubuntu) but contains no documentation of virtualization features (SVM/AMD-V, IOMMU), hypervisor compatibility (KVM/Hyper-V/VMware), or Docker/container workflows on this chip. Virtualization support is a fair question for a CPU/SoC but no evidence confirms it here.", "evidenceIds": [ "amd-ryzen-ai-max-plus-395-docs-8" ] }, { "productId": "apple-m4-max", "storyId": "agentic-agent-docs", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a chip/hardware platform, not an application with data and a UI that could surface AI-generated insights; this story applies to end-user software products, not silicon.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip, not an automation/agent platform; setting up autonomous background automations is a software/OS-level capability outside the scope of a silicon chip's evidence pack.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a software product with a built-in AI assistant persona to delegate tasks to — this axis is a category error for a silicon/SoC product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-headless", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not an AI agent or software product that could plug in MCP servers; MCP client integration is a wrong axis for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a software agent/platform that could host an MCP server; connecting an agent via an official MCP server is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-nl-commands", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-official-cli", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip, not a software product/platform that would ship its own CLI; the axis of an 'official CLI for AI-native workflows' is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-public-api", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip; issuing scoped API credentials for an agent is a software/IAM concern entirely outside a processor's product category.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "agentic-sdks", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Apple provides official developer SDKs (Metal, Metal 4, Core ML/PyTorch backend, GPU Neural Accelerators) that let developers build AI/ML applications targeting M4 Max hardware, as documented on developer.apple.com. However, evidence is purely vendor documentation with no hands-on developer corroboration of building against these SDKs, and the llms.txt probe returned 404, suggesting limited AI-native tooling depth. Missing for 10: independent developer corroboration of SDK usage, concrete code/API examples, and confirmation of AI-native discovery tooling (llms.txt).", "evidenceIds": [ "apple-m4-max-docs-10", "apple-m4-max-docs-12", "apple-m4-max-docs-13", "apple-m4-max-docs-11", "apple-m4-max-probe-1" ] }, { "productId": "apple-m4-max", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a service or platform that exposes event subscriptions; webhooks are a wrong-axis concept for a CPU/SoC product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "api-interactive-docs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a developer platform or API product; interactive API reference documentation is not a fair axis for a CPU/GPU chip.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "api-machine-spec", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not an API/service product; a machine-readable API spec (OpenAPI or similar) is not a relevant axis for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a software/service platform with sandbox vs. production data environments; sandbox testing is an application/service-layer concern, not a CPU/GPU silicon axis.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "api-versioning-policy", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip, not a software/service product with versioned developer APIs or a deprecation policy; this axis is a category error for a CPU/GPU product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip, not an application or agent capable of performing 'bulk operations across many items' as a user-facing automation workflow; this axis concerns software-level batch/automation features, which is a category error for a silicon chip.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not an automation/rules-engine platform; defining event-triggered automation rules is a software/OS-level capability outside the scope of a silicon product's evidence pack.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a workflow/automation platform; scheduling recurring jobs is a software orchestration capability entirely outside a CPU/SoC's product category.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns versioning, reviewing, and rolling back automations — a software/workflow-tooling capability, not something a hardware chip (M4 Max) provides. The axis is a category error for a CPU/GPU product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "developer-toolchain-maturity", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Apple's developer docs show clear tier-one tooling support (faster Xcode multi-simulator builds, Metal debugger, PyTorch/Metal ML backends, Metal 4 GPU acceleration APIs), indicating first-class OS/toolchain integration for Apple Silicon. However, community evidence notes real friction for other major dev workflows (e.g., UE game engine development still 'sluggish' on the platform), and there's no evidence pack coverage of broader compiler ecosystem maturity (LLVM/GCC, cross-platform toolchains) beyond Apple's own stack. Missing for 10: independent verification of general compiler/toolchain maturity beyond Xcode/Metal, and resolution of the UE/game-engine tooling gap.", "evidenceIds": [ "apple-m4-max-docs-3", "apple-m4-max-docs-10", "apple-m4-max-docs-11", "apple-m4-max-docs-12", "apple-m4-max-docs-13", "apple-m4-max-comm-4" ] }, { "productId": "apple-m4-max", "storyId": "expansion-io", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "Evidence documents Thunderbolt 5 bandwidth (120Gb/s) as an external connectivity spec, giving developers some concrete numbers to plan a dock/build around, but there is no documented PCIe generation/lane count, no SSD/storage throughput specs, and no first-party I/O architecture doc for M4 Max specifically. missing for 10: PCIe generation/lane count, internal storage throughput specs, a consolidated I/O/connectivity technical doc for M4 Max.", "evidenceIds": [ "apple-m4-max-docs-4", "apple-m4-max-comm-2" ] }, { "productId": "apple-m4-max", "storyId": "high-fps-gaming", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Apple's docs make a vendor gaming claim (M4 family GPU ray-tracing improving titles like Control) but there is no independent, hands-on game benchmark (FPS/frame-rate data) corroborating gaming performance; community commentary instead focuses on CPU benchmarks and notes game-dev engines like UE still run sluggishly on Mac, which is tangential rather than a direct FPS contradiction. missing for 10: independent third-party game FPS benchmarks, real game performance corroboration, comparison to discrete/console GPU class in actual gameplay.", "evidenceIds": [ "apple-m4-max-docs-8", "apple-m4-max-comm-4" ] }, { "productId": "apple-m4-max", "storyId": "local-llm-runtime-support", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Apple's own docs describe vendor AI stack support (Metal ML acceleration, PyTorch backend on Metal, GPU Neural Accelerators, Core ML/Neural Engine for on-device LLMs) which shows first-party silicon-targeted AI tooling, but there is no explicit documentation or mention of mainstream community runtimes like llama.cpp, MLX, or ONNX Runtime naming M4 Max support. missing for 10: explicit llama.cpp/MLX/ONNX Runtime support statements, independent benchmarks confirming these runtimes run well on M4 Max GPU/NPU.", "evidenceIds": [ "apple-m4-max-docs-2", "apple-m4-max-docs-5", "apple-m4-max-docs-10", "apple-m4-max-docs-12", "apple-m4-max-docs-13" ] }, { "productId": "apple-m4-max", "storyId": "media-engine-encode", "verdict": "partial", "quality": 7, "confidence": "medium", "rationale": "Apple's own docs confirm a dedicated Media Engine with two video encode engines and two ProRes accelerators, and cite real-time DaVinci Resolve de-noising as evidence of hardware-accelerated video workflows for creators. However, the pack never explicitly documents AV1 or HEVC hardware encode/decode support, nor independent benchmarks confirming streaming/encoding performance claims. Missing for 10: explicit AV1/HEVC hardware codec documentation, independent hands-on verification of encode/decode throughput for streaming use cases.", "evidenceIds": [ "apple-m4-max-docs-7", "apple-m4-max-docs-1" ] }, { "productId": "apple-m4-max", "storyId": "memory-spec-bandwidth", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains only marketing language (e.g., 'run 200-billion-parameter LLMs', 'battery life', 'video encode engines') with no vendor-published memory type (e.g., LPDDR5X), no stated capacity ceiling, and no bandwidth figure (e.g., GB/s) for the M4 Max chip itself. Community comments mention '192GB' but that's about a different SKU (Mac Studio) and is not vendor documentation. missing for 10: official memory type spec, capacity ceiling for M4 Max, and unified memory bandwidth number (GB/s) from Apple's own spec sheet.", "evidenceIds": [ "apple-m4-max-docs-2", "apple-m4-max-comm-2" ] }, { "productId": "apple-m4-max", "storyId": "multicore-build-performance", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Apple's docs claim faster Xcode builds/simulators and general CPU speed-up (1.8x vs M1) and heavy pro workloads, and a community Geekbench comparison shows M4 Max beating a 13900K, giving some independent corroboration. However, there is no documented core count/boost clock spec in the pack, and community comments raise doubts about Geekbench score verification and note it's 'sluggish' for some heavy dev workloads like UE, weakening the corroboration. Missing for 10: explicit core-count/boost-clock spec sheet, verified independent multi-core compile/build benchmarks, and resolution of the Geekbench verification skepticism.", "evidenceIds": [ "apple-m4-max-docs-3", "apple-m4-max-docs-9", "apple-m4-max-comm-1", "apple-m4-max-comm-3", "apple-m4-max-comm-4" ] }, { "productId": "apple-m4-max", "storyId": "npu-developer-access", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "Evidence confirms an official Neural Engine and shipping SDK/runtime (Core ML, Metal 4 GPU Neural Accelerators, PyTorch backends) for on-device ML acceleration, but nowhere in the pack is a specific TOPS figure with stated precision published for the M4 Max Neural Engine — only qualitative claims like 'faster Neural Engine' and 'blazing speed'. Missing for 10: a published TOPS number with precision (e.g., INT8/FP16) for the Neural Engine, independent benchmarking of NPU throughput.", "evidenceIds": [ "apple-m4-max-docs-5", "apple-m4-max-docs-12", "apple-m4-max-docs-13", "apple-m4-max-docs-10", "apple-m4-max-docs-2" ] }, { "productId": "apple-m4-max", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip, not a software product with a UI/API surface; the concept of API-vs-UI feature parity is a category error for this product type.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip, not a data-hosting service or application that stores user data; 'exporting data in open formats' is a category error for a CPU/SoC product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "openness-open-license", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a proprietary hardware chip; source code openness is not an applicable axis for a physical silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a hosted software product/service; 'self-hosting the core product' is a category error for a CPU/GPU chip design.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Max is a hardware chip, not a data-storage or cloud service; data residency/region selection is not an applicable axis for a CPU/GPU silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "privacy-no-training", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "M4 Max is a hardware chip, not a data-processing/AI-service platform that trains models on user data; preventing data-use-for-training is a policy axis for cloud/SaaS AI products, not a chip's local compute capability.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The Apple M4 Max is a hardware chip, not a data-handling service or AI platform with data retention/deletion controls; this axis applies to software/cloud products, not silicon.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Max is a hardware chip, not a software/service product with telemetry settings a user could opt out of; this privacy-posture/telemetry axis is a category error for a silicon chip.", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "published-spec-sheet", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "All evidence items are marketing-style claims ('rips through workloads', 'blazing speed', 'ultimate choice for video professionals') with no clock speeds, power/wattage figures, memory bandwidth numbers, or AI TOPS values with stated test conditions — the exact opposite of what the story requests. Community items are benchmark discussions, not vendor spec disclosures, and a llms.txt probe returned 404.", "evidenceIds": [ "apple-m4-max-docs-1", "apple-m4-max-docs-2", "apple-m4-max-docs-6", "apple-m4-max-docs-9", "apple-m4-max-comm-3" ] }, { "productId": "apple-m4-max", "storyId": "run-70b-local-llm", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Apple's own docs state the M4 Max's unified memory and Neural Engine let developers 'easily interact with large language models that have nearly 200 billion parameters,' which implies more than enough addressable memory for a 70B-class quantized model. However, no published memory-bandwidth figures (GB/s) are in the evidence pack, and there is no independent or hands-on benchmark confirming actual local 70B inference throughput — community discussion focuses on CPU/GPU benchmarks and SKU pricing, not LLM inference specifics. missing for 10: published memory bandwidth specs, independent/hands-on verification of running a 70B-class quantized model locally.", "evidenceIds": [ "apple-m4-max-docs-2", "apple-m4-max-comm-2" ] }, { "productId": "apple-m4-max", "storyId": "single-thread-responsiveness", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "One independent Geekbench-based community comment claims M4 Max 'absolutely shits on' a 13900K, offering hands-on single-core benchmark evidence beyond marketing claims, and Apple's own docs emphasize real-world responsiveness (e.g., real-time de-noising, fast multitasking). However, another commenter questions Geekbench score verification and a separate thread notes 'nowhere near single-CPU performance' for a related chip, adding some ambiguity; missing for 10: a rigorous, verified independent single-thread benchmark table (e.g., Cinebench/Geekbench single-core scores vs competitors) and resolution of the verification skepticism.", "evidenceIds": [ "apple-m4-max-comm-1", "apple-m4-max-comm-3", "apple-m4-max-docs-1", "apple-m4-max-docs-9" ] }, { "productId": "apple-m4-max", "storyId": "socket-upgrade-path", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-max", "storyId": "sustained-perf-per-watt", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Apple's docs assert energy efficiency and exceptional battery life alongside pro-workload performance (e.g., real-time RAW de-noising), but there are no documented power envelope figures (watts, sustained clocks) nor independent third-party testing of sustained performance-per-watt during long renders/exports. Community threads focus on raw Geekbench comparisons and skepticism about benchmark validity, not throttling behavior. Missing for 10: explicit power envelope specs, independent sustained-load/thermal throttling benchmarks, and real-world creator render tests confirming no throttling.", "evidenceIds": [ "apple-m4-max-docs-6", "apple-m4-max-docs-1", "apple-m4-max-comm-3" ] }, { "productId": "apple-m4-max", "storyId": "thin-quiet-battery", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "M4 Max targets high-end MacBook Pro/Mac Studio designs, not fanless or ultra-low-power machines, and the only battery-life claim (apple-m4-max-docs-6) is vague marketing language with no concrete battery-life benchmarks; community commentary (apple-m4-max-comm-7) explicitly notes the absence of any real battery-run-time data. Missing for 10: evidence of a fanless/thin M4 Max design, independent battery-life benchmarks or hours-of-use figures.", "evidenceIds": [ "apple-m4-max-docs-6", "apple-m4-max-comm-7" ] }, { "productId": "apple-m4-max", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "No evidence in the pack addresses virtualization, hypervisors (Virtualization.framework, UTM, Parallels), or Docker/container workflows on M4 Max; all docs focus on media, ML, and general performance claims.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-agent-docs", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a hardware chip, not a data application or product that surfaces AI-generated insights from user data; it merely provides silicon for others to run ML workloads. This story applies to end-user data products, not to a CPU/SoC, so the axis is a category error here.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not an automation/agent platform; setting up background autonomous automations is an OS/software-level capability entirely outside this product's category (a chip cannot itself 'set up' automations).", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a hardware chip, not an application or assistant product; it has no built-in AI assistant UI to delegate tasks to — it merely accelerates on-device AI/ML workloads run by other software (Apple Intelligence, MLX, Core ML). This story targets an agentic assistant feature, which is a wrong axis for a silicon chip product.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-headless", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not a software agent or platform that could plug in MCP servers; this axis is a category error for silicon hardware.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not an agent or software platform that could host an MCP server; the axis is a category error for this product type.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-nl-commands", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-official-cli", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not a software product/agent that could ship its own official CLI; the CLI axis is a category error for a silicon chip.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-public-api", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not an API/service platform that issues credentials for agents; scoped API credential issuance is entirely outside its product category.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "agentic-sdks", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Apple documents several official SDKs/frameworks developers can build against on M4 Pro hardware — Metal (GPU compute/ML), Core ML, MLX, and PyTorch backend support — giving AI-native developers real official APIs to target. However, the evidence is purely first-party marketing/dev-portal blurbs with no independent hands-on corroboration of building an AI app, and a probe shows no llms.txt/AI-specific docs endpoint exists. Missing for 10: independent developer reports of building against these SDKs, deeper API reference evidence, and an AI-specific documentation surface (llms.txt returned 404).", "evidenceIds": [ "apple-m4-pro-docs-6", "apple-m4-pro-docs-7", "apple-m4-pro-docs-8", "apple-m4-pro-docs-9", "apple-m4-pro-docs-10", "apple-m4-pro-probe-1" ] }, { "productId": "apple-m4-pro", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a hardware chip, not a service or platform with an event system; webhooks are a category error for this product type.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "api-interactive-docs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not a developer API/service product; an interactive API reference with runnable examples is a category error for this axis.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "api-machine-spec", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not an API/service product; a machine-readable API spec is a category mismatch for a silicon chip.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not a software/service product that provides sandbox environments for testing against production data; this axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "api-versioning-policy", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not an API/software service; versioned APIs with deprecation policies is a category error for this product type.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a hardware chip, not an application or interface that performs 'bulk operations across items'; this automation-depth story applies to software/agent tooling, not a silicon component.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not an automation/rules platform; defining event-triggered automation rules is a software/OS-level capability entirely outside the scope of a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a hardware chip, not a workflow/automation platform; scheduling recurring jobs is an OS/software-level capability entirely outside the scope of a silicon product, making this a category error rather than a missing feature.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not an automation/workflow platform; versioning, reviewing, and rolling back automations is not an applicable axis for a CPU/SoC product.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "developer-toolchain-maturity", "verdict": "partial", "quality": 7, "confidence": "medium", "rationale": "First-party docs show deep OS/tooling integration (Xcode, Metal, Core ML, MLX, PyTorch backend support) confirming Apple treats the architecture as a first-class target for building, debugging, and ML workloads. However, there's no explicit evidence of compiler-level optimization guidance (e.g., LLVM/Clang tuning docs) or independent developer corroboration of tooling maturity beyond Apple's own marketing pages. Missing for 10: dedicated compiler/optimization-guide documentation, independent hands-on developer confirmation of toolchain maturity.", "evidenceIds": [ "apple-m4-pro-docs-1", "apple-m4-pro-docs-6", "apple-m4-pro-docs-7", "apple-m4-pro-docs-8", "apple-m4-pro-docs-9", "apple-m4-pro-docs-10" ] }, { "productId": "apple-m4-pro", "storyId": "expansion-io", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "Only Thunderbolt 5 external connectivity (up to 120Gb/s) is documented; there is no mention of PCIe generation/lane counts, internal SSD/storage throughput specs, or a dock/build planning guide. missing for 10: PCIe generation and lane count details, internal storage/SSD bandwidth specs, multi-monitor/dock topology documentation, independent I/O benchmarking.", "evidenceIds": [ "apple-m4-pro-docs-2" ] }, { "productId": "apple-m4-pro", "storyId": "high-fps-gaming", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "Only a vague vendor line about the M4 GPU's ray-tracing making 'games like Control look more compelling' exists; there are no frame-rate figures, GPU-class comparisons, or independent game benchmarks to corroborate any gaming performance claim, and community comments merely question how it compares to RTX GPUs without providing data.", "evidenceIds": [ "apple-m4-pro-docs-4", "apple-m4-pro-comm-3" ] }, { "productId": "apple-m4-pro", "storyId": "local-llm-runtime-support", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Apple documents MLX, Core ML, Metal/PyTorch backend support explicitly targeting Apple Silicon GPU/Neural Engine, showing first-party AI stack support for the M4 Pro's compute units. However, there is no explicit mention of llama.cpp or ONNX Runtime support, no benchmarks/independent hands-on confirmation of local LLM inference performance, and the developer.apple.com llms.txt probe 404s. Missing for 10: explicit llama.cpp/ONNX Runtime documentation or compatibility statements, independent hands-on validation of local-AI runtime performance on M4 Pro specifically.", "evidenceIds": [ "apple-m4-pro-docs-5", "apple-m4-pro-docs-8", "apple-m4-pro-docs-9", "apple-m4-pro-docs-10", "apple-m4-pro-probe-1" ] }, { "productId": "apple-m4-pro", "storyId": "media-engine-encode", "verdict": "none", "quality": 0, "confidence": "low", "rationale": "The evidence pack contains no mention of hardware media engines, encode/decode support, AV1, HEVC, or ProRes acceleration for M4 Pro — only GPU ray tracing, ML frameworks, and connectivity are documented.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "memory-spec-bandwidth", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains no mention of M4 Pro's memory type, capacity ceiling, or bandwidth figures (e.g., unified memory type, GB/s bandwidth, max RAM configurations) — only marketing generalities about performance, GPU, Thunderbolt speed, and ML frameworks. Missing for 10: memory type spec, capacity ceiling numbers, bandwidth figure or spec detail to derive it.", "evidenceIds": [ "apple-m4-pro-docs-1", "apple-m4-pro-docs-2", "apple-m4-pro-docs-3" ] }, { "productId": "apple-m4-pro", "storyId": "multicore-build-performance", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains only marketing generalities about 'stunning performance' and Xcode build speed claims, with no documented core counts, boost clock behavior, or independent multi-core benchmark data; community comments are skeptical or comparative but supply no corroborating benchmark numbers.", "evidenceIds": [ "apple-m4-pro-docs-1", "apple-m4-pro-docs-3", "apple-m4-pro-comm-4", "apple-m4-pro-comm-6" ] }, { "productId": "apple-m4-pro", "storyId": "npu-developer-access", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "Evidence confirms a Neural Engine ('faster Neural Engine of the M4 family') and multiple official, shipping SDKs/runtimes (Core ML, MLX, Metal ML acceleration, PyTorch backend) that developers can use today. However, no evidence anywhere in the pack publishes a TOPS figure or states the precision for the M4 Pro's Neural Engine, which the story explicitly requires. Missing for 10: published TOPS number, stated precision (e.g., INT8/FP16) for the Neural Engine, independent benchmark corroborating throughput.", "evidenceIds": [ "apple-m4-pro-docs-5", "apple-m4-pro-docs-9", "apple-m4-pro-docs-10", "apple-m4-pro-docs-8" ] }, { "productId": "apple-m4-pro", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a hardware chip, not a software product with a UI/API surface — the concept of API-vs-UI parity is a category error for silicon.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not a data/service platform that stores user data; the concept of 'exporting data and leaving' is a category error for a CPU/SoC.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "openness-open-license", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a proprietary hardware chip; there is no source code to disclose under an open license, so this openness axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a physical chip, not a hosted service or software product; 'self-hosting the core product' is not a meaningful axis for silicon hardware.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The M4 Pro is a hardware chip, not a data storage/cloud service; data residency/region selection is a category error for this product type.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "privacy-no-training", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M4 Pro is a hardware chip, not a data-handling AI service or cloud training pipeline; the question of preventing user data from being used to train AI models is a wrong axis for a silicon product, though it enables on-device/local model execution which is a related but distinct capability.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The Apple M4 Pro is a hardware chip, not a data service or AI platform with data retention/deletion policies to control; this axis applies to software/services handling user data, not to a silicon chip.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "M4 Pro is a hardware chip, not a software product or service that could collect or expose telemetry/usage-tracking settings; opting out of telemetry is not an applicable axis for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "published-spec-sheet", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains only marketing language ('stunning performance', 'blazing speed', 'legendary power efficiency') with no published clock speeds, power/wattage figures, memory bandwidth specs, or AI TOPS numbers with defined test conditions. Community comments explicitly call out the lack of transparent, apples-to-apples benchmarking ('Why aren't they benching it against the M3?', 'grasping for a headline... why not compare apples to apples'), reinforcing that no real spec sheet is provided.", "evidenceIds": [ "apple-m4-pro-docs-1", "apple-m4-pro-docs-3", "apple-m4-pro-docs-5", "apple-m4-pro-comm-2", "apple-m4-pro-comm-4", "apple-m4-pro-comm-6" ] }, { "productId": "apple-m4-pro", "storyId": "run-70b-local-llm", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Evidence shows Apple Silicon has ML frameworks (MLX, PyTorch via Metal) suited for local model work, and community chatter references running LLMs locally as a real use case, but no published memory bandwidth figures or unified memory capacity numbers for M4 Pro are present in the pack, nor any concrete 70B-class benchmark. missing for 10: published memory bandwidth spec, max unified memory config, hands-on 70B quantized inference benchmark/tokens-per-second data.", "evidenceIds": [ "apple-m4-pro-docs-9", "apple-m4-pro-docs-8", "apple-m4-pro-comm-5" ] }, { "productId": "apple-m4-pro", "storyId": "single-thread-responsiveness", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains only vendor marketing language about general performance gains (docs-1/3) and community comments questioning or skeptical of benchmarking methodology (comm-2, comm-4, comm-6), but no independent single-thread benchmark data (e.g., Geekbench single-core scores) is cited anywhere to substantiate the specific claim of leading single-thread performance.", "evidenceIds": [ "apple-m4-pro-docs-1", "apple-m4-pro-docs-3", "apple-m4-pro-comm-2", "apple-m4-pro-comm-4", "apple-m4-pro-comm-6" ] }, { "productId": "apple-m4-pro", "storyId": "socket-upgrade-path", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m4-pro", "storyId": "sustained-perf-per-watt", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "Apple's marketing repeatedly claims 'legendary power efficiency' and faster rendering/exports (ray tracing, ML acceleration), but there's no documented sustained power envelope (TDP under load) or independent thermal/throttling benchmarks in the pack. Community comments even push back on efficiency comparison claims as 'grasping for a headline' and question benchmark methodology, though this doesn't rise to a concrete contradiction of sustained-render throttling. missing for 10: independent long-render/export sustained benchmark data, documented thermal/power envelope specs, third-party throttling tests.", "evidenceIds": [ "apple-m4-pro-docs-3", "apple-m4-pro-docs-4", "apple-m4-pro-comm-6" ] }, { "productId": "apple-m4-pro", "storyId": "thin-quiet-battery", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence only offers a generic 'legendary power efficiency' marketing line (apple-m4-pro-docs-3) with no battery-life benchmarks, no mention of fanless designs, and no quiet-operation claims specific to M4 Pro (which typically ships in fan-equipped MacBook Pro/Mac mini/Studio models). Community comments even push back on Apple's efficiency comparison methodology (apple-m4-pro-comm-6), and no independent battery-life data is cited. Missing for 10: fanless/low-power device pairing evidence, credible battery-life benchmarks, independent corroboration of efficiency claims.", "evidenceIds": [ "apple-m4-pro-docs-3", "apple-m4-pro-comm-6" ] }, { "productId": "apple-m4-pro", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "low", "rationale": "No evidence in the pack addresses virtualization, hypervisors (e.g., Virtualization.framework, Parallels, UTM), or Docker/container workflows on M4 Pro; docs focus on Xcode simulators, Thunderbolt, GPU, and ML frameworks. Missing for 10: any mention of hypervisor support, Docker Desktop/Rosetta virtualization, or independent benchmarks of VM/container performance on M4 Pro.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-agent-docs", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a documentation site or SaaS product; the probe explicitly shows no llms.txt exists at developer.apple.com (404), and there is no evidence of agent-oriented docs. Since this axis is plausible for a product with developer documentation but no such artifact exists, it is 'none' rather than 'na'.", "evidenceIds": [ "apple-m5-probe-1" ] }, { "productId": "apple-m5", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a silicon chip, not an end-user application with its own data surface; it accelerates AI workloads in other apps (Photoshop, Draw Things, Core ML apps) but has no product interface where a user's own data lives and gets AI-generated insights/suggestions. This is a category mismatch — the axis belongs to software products, not a processor.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software/automation platform; setting up autonomous background automations is an OS/app-level capability outside the scope of a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software product with a user-facing assistant; it enables AI workloads via frameworks but does not itself deliver a 'built-in AI assistant to delegate tasks to' — this is a category error for a silicon chip.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-headless", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software agent or platform that can plug into MCP servers; connecting MCP tools is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not an agent or service platform capable of hosting/connecting via an MCP server; this axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-nl-commands", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-official-cli", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software product/platform that would ship a CLI tool; this axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-public-api", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "Apple documents public developer APIs (Metal 4 Tensor APIs for Neural Accelerators, Core ML, Foundation Models framework) that let developers program the M5's AI hardware, but this is a hardware/developer-framework API, not an agentic API meant for an 'AI-native user' to drive the product directly. missing for 10: no evidence of an agent-facing/programmatic control API for the chip itself, no llms.txt or agent-oriented API docs (llms.txt probe returned 404), no independent corroboration of AI agents actually invoking these APIs.", "evidenceIds": [ "apple-m5-docs-1", "apple-m5-docs-2", "apple-m5-docs-4", "apple-m5-docs-9", "apple-m5-probe-1" ] }, { "productId": "apple-m5", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not an identity/access-management or API platform; scoped credential issuance for agents is a software/IAM concern entirely outside a silicon product's category.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "agentic-sdks", "verdict": "partial", "quality": 7, "confidence": "medium", "rationale": "Apple documents official SDKs (Metal 4 Tensor APIs/Neural Accelerators, Core ML, Metal Performance Shaders, Foundation Models framework, PyTorch-Metal backend) that AI-native developers can build against on M5 hardware, giving clear first-party API surfaces. However a community comment flags that Apple's ML libraries are 'insular and disconnected from the rest of the industry,' a real caveat on ecosystem openness rather than a functional failure. Missing for 10: independent hands-on developer reports building real AI apps with these SDKs, and clearer documentation/tutorials beyond marketing pages.", "evidenceIds": [ "apple-m5-docs-1", "apple-m5-docs-2", "apple-m5-docs-4", "apple-m5-docs-9", "apple-m5-docs-11", "apple-m5-docs-12", "apple-m5-comm-6" ] }, { "productId": "apple-m5", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a service or API platform; webhook event subscriptions are a software/service integration concept that doesn't apply to a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "api-interactive-docs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a developer API/SDK product with its own interactive documentation portal; 'runnable examples in an interactive API reference' is a category error for a silicon product—this axis belongs to software platforms/SDKs, not chips.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "api-machine-spec", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a service or API-driven product; a machine-readable OpenAPI spec is a category error for a silicon chip.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software/service platform with sandbox/production environments; sandboxed testing against production data is not an axis applicable to a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "api-versioning-policy", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software service or platform with versioned APIs and a deprecation policy for developers to rely on; this axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software/agent tool with a UI or API for performing bulk operations across items; this automation-depth/bulk-operations story is a category error for a chip product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software platform for defining event-triggered automation rules; this automation/rules-engine axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software platform or agent that schedules jobs/workflows; job scheduling is outside the scope of a silicon product and is a wrong-axis question for this category.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not an automation/workflow platform; versioning, reviewing, and rolling back automations is a software/orchestration capability entirely outside the scope of a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "developer-toolchain-maturity", "verdict": "full", "quality": 8, "confidence": "medium", "rationale": "Apple documents mature first-party tooling for the M-series/ARM64 target: Metal 4 with Tensor APIs and a dedicated Metal debugger, Core ML and Metal Performance Shaders auto-acceleration, a PyTorch GPU backend, and the Foundation Models framework getting native speedups — all signs of tier-one OS/toolchain integration on Apple Silicon. Community commentary corroborates real performance gains (10M TPS in a C benchmark, GPU/CPU uplifts) though one comment criticizes Apple's ML libraries as 'insular and disconnected from the rest of the industry,' a minor ecosystem caveat. Missing for 10: independent compiler-maturity benchmarks (LLVM/clang codegen quality vs x86), explicit official optimization guides beyond marketing copy, and broader third-party tooling parity evidence.", "evidenceIds": [ "apple-m5-docs-1", "apple-m5-docs-2", "apple-m5-docs-4", "apple-m5-docs-8", "apple-m5-docs-9", "apple-m5-docs-11", "apple-m5-comm-6", "apple-m5-comm-14" ] }, { "productId": "apple-m5", "storyId": "expansion-io", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains only display-resolution specs and memory bandwidth figures, with no documented PCIe generation/lane count, SSD/storage throughput specs, or Thunderbolt/USB port specifications that a developer could plan a dock or expansion setup around.", "evidenceIds": [ "apple-m5-docs-13", "apple-m5-docs-14", "apple-m5-docs-15" ] }, { "productId": "apple-m5", "storyId": "high-fps-gaming", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Apple's own materials claim gaming-relevant GPU gains (second-gen dynamic caching, 'smoother gameplay,' hardware ray tracing, up to 4x GPU compute vs M4), but the evidence pack contains no independent frame-rate or game-specific benchmarks — community discussion focuses on CPU Geekbench scores, LLM throughput, and memory bandwidth, not actual game FPS testing. Missing for 10: independent game benchmark results (FPS/frame-time comparisons), third-party reviewer corroboration of gaming claims, real-world title testing beyond synthetic CPU scores.", "evidenceIds": [ "apple-m5-docs-7", "apple-m5-docs-15", "apple-m5-comm-8", "apple-m5-comm-12" ] }, { "productId": "apple-m5", "storyId": "local-llm-runtime-support", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Apple documents its own AI stack (Core ML, Metal Performance Shaders, Metal 4 Tensor APIs, PyTorch backend via Metal, GPU Neural Accelerators) explicitly supporting M5's CPU/GPU/NPU, and community evidence confirms real-world LLM/diffusion workloads (webAI, Draw Things, Qwen models) running locally on the chip. However, no evidence explicitly ties llama.cpp, MLX, or ONNX Runtime by name to M5-specific support, so mainstream cross-vendor runtime targeting is only inferred, not documented. missing for 10: explicit llama.cpp/MLX/ONNX Runtime documentation naming M5 support, independent benchmark confirming these runtimes exploit M5's Neural Accelerators.", "evidenceIds": [ "apple-m5-docs-1", "apple-m5-docs-2", "apple-m5-docs-3", "apple-m5-docs-9", "apple-m5-docs-11", "apple-m5-comm-2", "apple-m5-comm-3" ] }, { "productId": "apple-m5", "storyId": "media-engine-encode", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains no mention of a dedicated hardware media engine, nor any reference to AV1, HEVC, or ProRes encode/decode capabilities on M5 — it only covers GPU compute, Neural Accelerators, ML frameworks, and RAM/bandwidth debates. This is a fair axis for a media-focused Apple chip, but none of the provided docs or community posts document hardware video encode/decode support, so it cannot be credited as full/partial/disputed.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "memory-spec-bandwidth", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Apple's spec page explicitly states 153GB/s memory bandwidth for the base M5 and describes a unified memory architecture, giving a developer a concrete bandwidth figure and general memory type concept, but it lacks a stated memory technology (e.g., LPDDR generation) and does not publish a capacity ceiling — the 32GB max cited comes only from community discussion, not vendor docs. missing for 10: vendor-stated memory technology/type, vendor-published max capacity configuration, independent corroboration of the bandwidth figure.", "evidenceIds": [ "apple-m5-docs-15", "apple-m5-docs-5", "apple-m5-comm-4", "apple-m5-comm-9" ] }, { "productId": "apple-m5", "storyId": "multicore-build-performance", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Apple documents GPU/Neural Engine core counts and memory bandwidth for M5 (apple-m5-docs-15) and independent Geekbench multi-core benchmarks show real gains (~15% multi-core uplift, comm-12/13) plus a multithreaded CPU performance claim (comm-8) and a throughput comparison (comm-14), giving some corroboration for parallel workload speed. However, Apple's own materials do not publish CPU core count, clock speed, or boost behavior for M5 (confirmed by apple-m5-probe-rt-1 noting no clock/TDP spec sheet exists), and no benchmarks specifically target compiling large codebases or dev toolchains. Missing for 10: documented CPU core count and boost/turbo clock specifics, compiler/build-workload benchmarks, and Mac-specific (not just iPad) independent multi-core corroboration.", "evidenceIds": [ "apple-m5-docs-15", "apple-m5-comm-8", "apple-m5-comm-12", "apple-m5-comm-13", "apple-m5-comm-14", "apple-m5-probe-rt-1" ] }, { "productId": "apple-m5", "storyId": "npu-developer-access", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Apple documents a 16-core Neural Engine plus GPU Neural Accelerators and ships real developer runtimes today (Core ML, Metal Performance Shaders, Metal 4 Tensor APIs, PyTorch backend), satisfying the 'official SDK/runtime ships today' half of the story. However, no published TOPS figure (with precision stated) for the Neural Engine or Neural Accelerators appears anywhere in the evidence pack — Apple's newsroom and spec pages list core counts and memory bandwidth but omit any TOPS metric. Missing for 10: a published TOPS number with stated precision (e.g., INT8/FP16) for the M5 Neural Engine or Neural Accelerators, and independent verification of that figure.", "evidenceIds": [ "apple-m5-docs-1", "apple-m5-docs-2", "apple-m5-docs-9", "apple-m5-docs-15", "apple-m5-probe-rt-1" ] }, { "productId": "apple-m5", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a software product with a UI/API duality; 'API vs UI parity' is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a data storage/service platform; there is no user data or account to export in open formats. Data export/portability is a category error for a silicon product's axis.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "openness-open-license", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a proprietary hardware chip; there is no source code to publish under an open license, making 'read the product's source under an open license' a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a hostable software service or platform; 'self-hosting the core product' is a category error for a chip axis — devices containing it are simply owned/purchased, not 'self-hosted' in the software sense.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a data storage/cloud service; data residency/region selection is a category error for a silicon product and applies to cloud platforms, not on-device compute silicon.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "privacy-no-training", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a service or platform that processes user data for AI training; data-use/training-opt-out policies are a software/service-layer concern, not a chip-level axis.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a data-processing service or app with data retention/deletion controls; the on-device processing enabled by M5 means data locality is a hardware side-effect, not a governance feature the chip itself offers. This axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Apple M5 is a hardware chip, not a service or software product that collects telemetry/usage data from users in a way that would require an opt-out control; this axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "published-spec-sheet", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "Apple's own M5 materials list core counts and unified memory bandwidth (153GB/s) but omit clock speeds, TDP/power figures, and AI TOPS numbers with test conditions — instead using relative marketing comparisons like 'up to 4x GPU compute' or '30% higher graphics performance' (apple-m5-comm-8). The runtime probe explicitly confirms Apple publishes no clock-speed, TDP, or ARK-style spec sheet, with the newsroom post serving as the only 'spec disclosure' (apple-m5-probe-rt-1).", "evidenceIds": [ "apple-m5-docs-15", "apple-m5-comm-8", "apple-m5-probe-rt-1", "apple-m5-probe-1" ] }, { "productId": "apple-m5", "storyId": "run-70b-local-llm", "verdict": "disputed", "quality": 4, "confidence": "high", "rationale": "Apple markets M5's unified memory as enabling 'larger AI models completely on device' (apple-m5-docs-5), but the shipping base M5 specs show only 32GB max RAM and 153GB/s bandwidth (apple-m5-docs-15), and community hands-on commentary explicitly states this is 'not enough to run viable open source LLM models properly' and that 32GB is 'an even bigger problem' for real workloads (apple-m5-comm-1, apple-m5-comm-4, apple-m5-comm-9). Higher-memory Pro/Max variants needed for 70B-class quantized models are not yet available. Missing for 10: published Pro/Max M5 specs with sufficient memory/bandwidth, and independent benchmarks of actual 70B-class quantized inference throughput.", "evidenceIds": [ "apple-m5-docs-5", "apple-m5-docs-15", "apple-m5-comm-1", "apple-m5-comm-4", "apple-m5-comm-9", "apple-m5-comm-3" ] }, { "productId": "apple-m5", "storyId": "single-thread-responsiveness", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Independent leaked Geekbench benchmarks show M5's single-core score improving ~10-12% over M4 (e.g., 4133 vs 3748), giving real hands-on single-thread numbers rather than just Apple's peak-GHz marketing. However, there's no independent comparison against competing power-user chips (AMD/Intel) to substantiate a 'leading' claim, and Apple's own docs focus on GPU/AI throughput rather than single-thread specs. Missing for 10: cross-vendor single-thread benchmark comparisons, sustained/interactive-workload latency testing, and independent reviewer verification beyond a leaked unboxing.", "evidenceIds": [ "apple-m5-comm-12", "apple-m5-comm-13", "apple-m5-comm-8" ] }, { "productId": "apple-m5", "storyId": "socket-upgrade-path", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "sustained-perf-per-watt", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "No documented power envelope (TDP/wattage) or independent sustained-load/thermal-throttling testing is present; evidence covers battery-video-hours, peak GPU/CPU speedup claims, and short benchmark scores, none of which address sustained render/export performance-per-watt over time.", "evidenceIds": [] }, { "productId": "apple-m5", "storyId": "thin-quiet-battery", "verdict": "full", "quality": 8, "confidence": "high", "rationale": "Apple's M5 ships in fanless iPad Pro and thin, fanless-adjacent MacBook Pro designs with documented all-day battery claims (up to 24 hours video streaming) and community benchmarks confirming real-world performance/efficiency gains over M4. Community discussion corroborates strong CPU efficiency and performance-per-watt improvements, consistent with Apple's power-efficiency-first chip design philosophy. missing for 10: independent third-party battery-life testing (e.g., reviewer runtime benchmarks) and explicit fanless-design confirmation for the specific M5 MacBook Pro SKU.", "evidenceIds": [ "apple-m5-docs-13", "apple-m5-docs-15", "apple-m5-comm-8", "apple-m5-comm-12", "apple-m5-comm-13" ] }, { "productId": "apple-m5", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack covers M5's AI/ML acceleration, GPU, Metal APIs, and general hardware specs, but contains no mention of virtualization support, hypervisor frameworks (e.g. Apple Hypervisor.framework, Parallels, UTM, VMware Fusion), or Docker/container workflows on M5. Missing for 10: documented virtualization framework support, hypervisor compatibility claims, Docker Desktop/container runtime performance data, and any developer or community confirmation of VM/container workflows on M5 silicon.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-agent-docs", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "A probe confirms Intel's site serves an llms.txt file (HTTP 200) with a short company description, so an agent could point at it, but the content is generic corporate boilerplate rather than product-specific or deeply agent-oriented documentation, and no OpenAPI/agent-friendly API docs were found. Missing for 10: product-specific llms.txt content, structured agent-facing docs beyond the generic snippet, and a working openapi.json.", "evidenceIds": [ "intel-core-ultra-7-258v-probe-1", "intel-core-ultra-7-258v-probe-2" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU/SoC product, not an application with user data to analyze; it enables AI features in other software (Copilot+, third-party apps) rather than itself surfacing insights from a user's data. The axis is a category error for a silicon component.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; setting up autonomous background automations is a software/agent-platform capability, not something a chip itself provides — wrong axis for this product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product, not an AI assistant application; Copilot+ voice features referenced are Microsoft's OS-level assistant, not a built-in assistant of the chip itself. Delegating tasks to a built-in AI assistant is a category error for a processor.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-headless", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product, not an agent or software platform capable of hosting MCP servers; MCP plug-in capability is a wrong axis for a processor product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; connecting an agent via an official MCP server is a software/service integration axis that doesn't apply to a physical processor SKU.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-nl-commands", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "The chip's marketing highlights Copilot+ voice-command features ('Say it and Copilot+ helps do it... Use voice commands to get answers, edit content, and turn ideas into reality'), suggesting natural-language operation is enabled at the platform level. However, this is a vendor claim tied to the broader Copilot+ PC ecosystem rather than a documented, hands-on demonstration of the processor itself enabling NL command execution. Missing for 10: independent verification of voice/NL command reliability, technical detail on how the chip enables this beyond marketing copy, and broader agentic command scope beyond voice assistant tasks.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-7" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-official-cli", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product, not a software tool/agent platform; an 'official CLI' for AI-native workflows is a category mismatch for a processor SKU.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-public-api", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; scoped API credential issuance for agents is a software/IAM concern entirely outside a processor's product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-sdks", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Intel documents official developer SDKs/tools for this chip family—oneAPI, oneDNN, PyTorch optimizations, VTune Profiler, and SYCL interoperability—that let AI-native developers build and optimize LLM/image-gen workloads on Core Ultra processors and Arc GPUs. However, evidence is limited to vendor product pages with no code samples, API references, or independent developer corroboration of hands-on SDK usage. Missing for 10: linked SDK documentation/quickstarts, independent developer reports of building against these SDKs, and details on NPU-specific developer APIs beyond marketing copy.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-10", "intel-core-ultra-7-258v-docs-11", "intel-core-ultra-7-258v-docs-12" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware; webhooks/event subscriptions are a software/API integration concept that doesn't apply to a processor product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "api-interactive-docs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; an interactive API reference with runnable examples is a software/developer-platform axis that does not apply to a physical processor SKU.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "api-machine-spec", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; there is no API surface to expose via OpenAPI spec, so this axis is a category error for the product type.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; sandbox testing environments separate from production data is a software/platform concept not applicable to a processor SKU.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "api-versioning-policy", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product, not an API/service platform; versioned APIs with deprecation policy is a wrong axis for a physical chip product.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; bulk operations across items is a software/application-layer capability, not something a processor itself ships as a feature — this is a category error for this product type.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; rule-based automation/event-trigger authoring is a software/platform-level capability entirely outside the scope of a silicon product's axis.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; scheduling recurring jobs/workflows is a software/automation-platform capability, not something a chip itself ships as a feature. The axis is a category error for a processor product.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; versioning, reviewing, and rolling back automations is a software/workflow-management capability entirely outside the scope of a processor's category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "developer-toolchain-maturity", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Intel provides official developer tooling (oneAPI, oneDNN, VTune Profiler, PyTorch optimizations, SYCL interoperability) targeting Core Ultra CPUs/GPUs/NPUs, showing real optimization guidance and tooling investment for this architecture. However, evidence is entirely vendor-sourced with no independent corroboration of compiler maturity, OS-level tier-one treatment, or broader ecosystem support (e.g., GCC/LLVM upstream status, Linux kernel support specifics). Missing for 10: independent/third-party confirmation of compiler maturity, explicit OS tier-one support statements, and broader ecosystem tooling beyond Intel's own oneAPI suite.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-10", "intel-core-ultra-7-258v-docs-11", "intel-core-ultra-7-258v-docs-12" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "expansion-io", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains only marketing copy about graphics, AI features, and gaming/creative use cases; there is no documentation of PCIe generation/lane counts, storage interface specs, or external connectivity (Thunderbolt/USB) details a developer could use to plan a build or dock setup.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "high-fps-gaming", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Vendor docs claim Arc graphics, XeSS 3 upscaling, and 'ultra-smooth FPS' for gaming, and list compatibility with major game stores, but there is no independent game benchmark data in the evidence pack to corroborate real-world frame rates or the iGPU class claims. missing for 10: independent/hands-on FPS benchmarks in real games, cache/boost behavior verification, comparative iGPU-class positioning against competitors.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-4", "intel-core-ultra-7-258v-docs-5", "intel-core-ultra-7-258v-docs-6" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "local-llm-runtime-support", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Intel's own oneAPI/oneDNN and PyTorch optimizations explicitly target Core Ultra Series 2 CPUs and Arc GPUs, and VTune profiler supports GPU/NPU analysis, showing vendor-stack support. However, there's no evidence of llama.cpp, MLX, or ONNX Runtime explicitly documenting support for this chip's CPU/GPU/NPU. Missing for 10: llama.cpp/ONNX Runtime/MLX documentation citing this exact silicon, NPU-specific runtime support evidence, independent benchmarks confirming real-world local-AI usage.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-10", "intel-core-ultra-7-258v-docs-11" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "media-engine-encode", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Docs confirm a dedicated Intel Xe Media Engine enabling simultaneous play/stream/edit with high-def video, but no specifics on codec support (AV1, HEVC, ProRes-class) or their encode/decode capabilities are documented. missing for 10: explicit codec support list (AV1/HEVC/ProRes), encode/decode performance specs, independent benchmarks.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-5", "intel-core-ultra-7-258v-docs-1" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "memory-spec-bandwidth", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "Evidence pack contains only marketing copy about AI features, gaming, and dev tools; no memory type (LPDDR5X), capacity ceiling, or bandwidth figures are cited anywhere in the pack.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "multicore-build-performance", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains only marketing copy about gaming, creative apps, and AI features plus generic developer-tool blurbs (oneDNN, VTune) — nothing documents core/thread counts, boost clocks, or independent multi-core compilation/parallel-job benchmarks for the 258V. missing for 10: documented core/thread counts and boost clock specs, independent multi-core benchmark results (e.g. Cinebench, compile-time tests), any developer-reported build performance data.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "npu-developer-access", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Evidence confirms a dedicated NPU ('low-power AI engines') and an official developer runtime/SDK path (oneAPI, oneDNN, PyTorch optimizations, VTune NPU profiling support) that ships today, satisfying the SDK/runtime part of the story. However, no citation states a published TOPS figure or specifies the precision (e.g., INT8) for the NPU, which is a core requirement of the story. Missing for 10: published TOPS number, stated precision, and independent corroboration of the NPU spec.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-8", "intel-core-ultra-7-258v-docs-10", "intel-core-ultra-7-258v-docs-11" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product with no UI/API surface of its own; the 'API parity with UI' story is a category error for a physical processor.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product, not a data-storing service or SaaS platform; data export/portability is not an applicable axis for a processor.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "openness-open-license", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "The Core Ultra 7 258V is a physical CPU/hardware product; 'reading source under an open license' is a category error for a hardware chip (no source code artifact to license). This axis applies to software/code products, not silicon.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; 'self-hosting the core product' is a software-deployment axis that doesn't apply to a physical chip you already own/run locally by nature of purchase.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is a hardware component that runs locally on-device; it has no data storage/hosting service and thus no concept of data residency/region selection. This story applies to cloud or SaaS products, not a processor.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "privacy-no-training", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; data-training privacy controls (preventing user data from being used for AI model training) is a data-handling/service-policy axis that doesn't apply to a silicon component with no cloud data pipeline of its own.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; data retention/deletion controls are a data-governance/software feature axis that doesn't apply to a silicon chip's evidence pack.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product, not a service or application with user accounts, telemetry, or data collection that a user could opt into/out of in the software-privacy sense; the axis does not apply to a processor SKU.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "published-spec-sheet", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "All evidence entries are marketing-style feature blurbs (gaming, AI apps, voice commands, Bluetooth) rather than an actual spec sheet listing clocks, TDP/power, memory support, or AI TOPS with test conditions; no technical spec table or footnoted benchmark methodology is present in the pack.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-1", "intel-core-ultra-7-258v-docs-7", "intel-core-ultra-7-258v-docs-8", "intel-core-ultra-7-258v-docs-9" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "run-70b-local-llm", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains only generic Copilot+/AI-PC marketing and developer-tool blurbs (oneDNN, VTune, SYCL) with no published memory capacity, memory bandwidth, or any claim about running 70B-class quantized LLMs locally. Nothing addresses addressable memory size or bandwidth needed to judge local large-model feasibility.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-10", "intel-core-ultra-7-258v-docs-8" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "single-thread-responsiveness", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack contains only Intel marketing copy about GPU, AI, and battery features with no independent single-thread benchmark data (e.g., Cinebench single-core, Geekbench) to support the specific claim of leading interactive single-thread performance. Missing for 10: independent benchmark results, single-thread performance comparisons, third-party reviews validating responsiveness.", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "socket-upgrade-path", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "intel-core-ultra-7-258v", "storyId": "sustained-perf-per-watt", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "Evidence is limited to Intel marketing copy about creating/rendering and vague claims of 'intelligent power management' with no documented power envelope specs (TDP curves, sustained wattage) or any independent/third-party testing of sustained performance-per-watt during long renders or exports; missing for 10: documented power envelope tables, independent benchmark/testing showing sustained throughput under load without throttling.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-1", "intel-core-ultra-7-258v-docs-8" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "thin-quiet-battery", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "Intel's marketing copy gestures at all-day, unplugged use and low-power AI engines/power management, implying efficiency for thin-and-light designs, but there are no concrete battery-life hour claims, no mention of fanless designs, and no independent hands-on corroboration in the pack. Missing for 10: fanless/thin-chassis design examples, specific battery-life hour figures, independent reviewer benchmarks confirming all-day battery claims.", "evidenceIds": [ "intel-core-ultra-7-258v-docs-1", "intel-core-ultra-7-258v-docs-8", "intel-core-ultra-7-258v-docs-9" ] }, { "productId": "intel-core-ultra-7-258v", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "Evidence pack covers Intel Arc graphics, creative apps, gaming, and AI dev tools (oneDNN, VTune), but contains no mention of virtualization (VT-x/VT-d), hypervisor support, or Docker/container workflows on this chip.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-agent-docs", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Intel's corporate site does serve a machine-fetchable llms.txt (confirmed via probe returning HTTP 200 with a short company description), so an agent could be pointed at it, but the snippet is generic corporate boilerplate with no product-specific or agent-oriented documentation for the Core Ultra 9 285K itself, and no openapi/agent API endpoints were found. missing for 10: richer llms.txt content tailored to product docs, presence of llms-full.txt or structured agent-facing spec docs, independent confirmation the file is kept current.", "evidenceIds": [ "intel-core-ultra-9-285k-probe-1", "intel-core-ultra-9-285k-probe-2" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product, not an application or platform that itself surfaces AI-generated insights from user data; it provides underlying compute/frameworks (oneDNN, OpenVINO) for other software to build such features, but the CPU itself does not deliver in-product insights/suggestions. This is a wrong-axis question for a processor SKU.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product; setting up autonomous background automations is a software/agent-platform capability, not something a processor itself ships or delivers—wrong axis for this product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware, not an application with a built-in AI assistant/agent that can accept delegated tasks; this axis is a category error for a processor product. Voice command mentions refer to third-party software features enabled by the platform, not a built-in assistant shipped by Intel.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-headless", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware, not an agent or platform that connects to MCP servers; MCP tool-plugging is a software/agent-layer concept and not a fair axis for this product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; MCP server connectivity is a software/agent-ecosystem concept that doesn't apply to a physical processor's role in this axis.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-nl-commands", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Marketing copy claims 'voice commands to get answers, edit content, and turn ideas into reality,' suggesting some natural-language interaction on Core Ultra platforms, but this is a single vague marketing line with no product specifics, no named assistant, and no hands-on corroboration. Missing for 10: concrete details on which software/assistant enables this, independent verification it works as described, and evidence of broader NL command support beyond voice.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-7" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-official-cli", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product, not a developer tool or platform with a client ecosystem; 'official CLI' is a category error for a processor SKU rather than a missing feature.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-public-api", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU hardware product has no API credential/authorization system; scoped API credentials for agents is a software/platform axis, not applicable to a physical processor.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-sdks", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Intel documents official SDKs and toolkits (oneAPI, oneDNN, DPC++ Compatibility Tool, VTune Profiler) and lists supported AI frameworks (OpenVINO, DirectML, ONNX RT, WebNN) for the Core Ultra platform, which an AI-native developer could build against. However, this evidence is generic to the Core Ultra line rather than specific hands-on validation for the 285K, and there's no independent corroboration of developer experience with these SDKs. missing for 10: independent/hands-on validation of SDK usability, concrete code examples or developer testimonials, and confirmation these tools are specifically exercised on the 285K rather than just documented for the broader Core Ultra family.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-10", "intel-core-ultra-9-285k-docs-11", "intel-core-ultra-9-285k-docs-12", "intel-core-ultra-9-285k-docs-13" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware, not a service/platform with events or subscription APIs; webhooks are a wrong axis for this product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "api-interactive-docs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a physical CPU product, not an API/SaaS platform; there is no interactive API reference or runnable-examples concept applicable to it.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "api-machine-spec", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a physical CPU product, not an API/service; a machine-readable OpenAPI spec is a category error for this axis. The probe confirms no OpenAPI endpoint exists, but that's expected since Intel's website is not the product itself.", "evidenceIds": [ "intel-core-ultra-9-285k-probe-2" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns sandboxed test environments isolated from production data, which is a software/platform capability, not something a CPU product ships. The evidence pack covers hardware specs, gaming/creative performance, and developer tools like oneAPI, none of which relate to sandbox testing environments.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "api-versioning-policy", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU hardware product is not itself an API service; versioned APIs with a deprecation policy is a category error for this product type.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns AI-native bulk/automation operations across items, which is a software/workflow-orchestration axis; a CPU is hardware and does not itself perform 'bulk operations across items' — that's a category error for this product type.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns defining automation rules/triggers, which is a software/platform capability, not something a CPU hardware product ships. The Core Ultra 9 285K is a processor with no rule-engine or event-trigger feature—this axis is a category error for a hardware SKU.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware, not a workflow/orchestration platform; scheduling recurring jobs is a software/OS or automation-tool capability outside a processor's product category.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns software automation versioning/rollback workflows, which is entirely outside the scope of a CPU hardware product; the axis does not apply to a processor.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "developer-toolchain-maturity", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Intel provides substantive official developer tooling (oneAPI, VTune Profiler, DPC++ CUDA-to-SYCL migration, oneDNN/PyTorch optimizations, OpenVINO/DirectML/ONNX support) suggesting tier-one treatment for AI/HPC workloads. However, community evidence shows real platform-maturity friction: compiler segmentation faults tied to memory configuration, a 'messy' Arrow Lake Windows launch requiring OS/firmware fixes, and reports of severe performance regressions on newer Windows builds — undermining the 'mature, tier-one, no caveats' framing. Missing for 10: independent benchmarks confirming stable toolchain behavior across compilers (GCC/MSVC/LLVM) without workarounds, evidence of Linux distro-level tier-one support, and resolution confirmation for the reported crashes/perf regressions.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-10", "intel-core-ultra-9-285k-docs-11", "intel-core-ultra-9-285k-docs-12", "intel-core-ultra-9-285k-docs-13", "intel-core-ultra-9-285k-comm-1", "intel-core-ultra-9-285k-comm-4", "intel-core-ultra-9-285k-comm-6" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "expansion-io", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains no specifics on PCIe generation/lane counts, storage interface support, or external connectivity (USB/Thunderbolt) specs for the 285K platform — only marketing copy, memory/vPro/ECC details, and Linux/Windows performance reports. This axis clearly applies to a desktop CPU/platform story, but no documentation of I/O headroom is present, so it cannot be credited. Missing for 10: PCIe lane/generation breakdown, storage (M.2/NVMe) specs, USB/Thunderbolt connectivity details, chipset I/O documentation.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-13", "intel-core-ultra-9-285k-docs-14", "intel-core-ultra-9-285k-docs-15" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "high-fps-gaming", "verdict": "disputed", "quality": 3, "confidence": "high", "rationale": "Intel's marketing touts smooth FPS and GPU-class gaming features, but independent reviews directly contradict this for the 285K desktop chip: Tom's Hardware reports 'generational regression in gaming performance' making it worse than the prior-gen 14900K and worse value than AMD, and HN citations confirm it trails both the 14900K and 7800X3D in gaming benchmarks, with some Windows configs seeing 50% FPS drops. Missing for 10: any vendor-cited gaming benchmark specific to the 285K, and any independent benchmark showing it competitively winning frame-rate comparisons.", "evidenceIds": [ "intel-core-ultra-9-285k-comm-2", "intel-core-ultra-9-285k-comm-3", "intel-core-ultra-9-285k-comm-6", "intel-core-ultra-9-285k-docs-3" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "local-llm-runtime-support", "verdict": "full", "quality": 7, "confidence": "medium", "rationale": "Intel's own spec page explicitly lists AI software frameworks supported by the CPU—OpenVINO, ONNX Runtime, DirectML, WindowsML, WebNN—and Intel's developer docs describe oneAPI/oneDNN and PyTorch optimizations tuned for Core Ultra processors and Arc GPUs, directly naming mainstream local-AI runtimes as supported. Missing for 10: explicit llama.cpp/MLX mention, and independent hands-on confirmation that these runtimes actually run well on the 285K specifically (reviews focus on gaming/productivity benchmarks, not AI runtime performance).", "evidenceIds": [ "intel-core-ultra-9-285k-docs-13", "intel-core-ultra-9-285k-docs-10" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "media-engine-encode", "verdict": "partial", "quality": 3, "confidence": "low", "rationale": "Intel's marketing mentions an integrated 'Xe Media Engine' enabling simultaneous play/stream/edit with 'sharp, high-def video' and general Arc graphics support for editing/rendering, but the evidence pack never names specific codec support (AV1, HEVC, ProRes-class) for encode/decode on this chip. missing for 10: explicit documentation of AV1/HEVC hardware encode+decode, ProRes support, and any independent benchmark/hands-on verification of media engine performance.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-4", "intel-core-ultra-9-285k-docs-1", "intel-core-ultra-9-285k-docs-8" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "memory-spec-bandwidth", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "Evidence shows ECC memory support and vPro details from Intel's ARK spec page, and community reports confirm a rated DDR5 speed (DDR5-6400) and CUDIMM support, but no explicit vendor-published memory capacity ceiling or bandwidth figures are quoted in the pack. The probe confirms ARK has a 'machine-fetchable spec sheet' including memory support, but the actual numbers aren't captured here. missing for 10: explicit max memory capacity (GB), number of channels, and bandwidth (GB/s) figures from vendor docs.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-14", "intel-core-ultra-9-285k-comm-1", "intel-core-ultra-9-285k-comm-3", "intel-core-ultra-9-285k-probe-rt-1" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "multicore-build-performance", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Intel's ARK spec page (confirmed live via probe) documents core counts and boost clocks, and independent reviews (Tom's Hardware, Phoronix, HN discussion) corroborate strong multi-threaded productivity performance versus its predecessor, supporting compile/parallel-job workloads. However, the same independent sources show AMD's 9950X ahead in raw multi-core performance/perf-per-watt, and Phoronix reports real compiler segfaults tied to non-rated RAM speeds — a concrete caveat for compiling workloads. missing for 10: explicit quoted core-count/boost-clock figures in the evidence pack itself, quantitative independent multi-core benchmark numbers (only qualitative 'productivity performance' claims), and confirmation the RAM-related compiler stability issue is fully resolved across configurations.", "evidenceIds": [ "intel-core-ultra-9-285k-probe-rt-1", "intel-core-ultra-9-285k-comm-2", "intel-core-ultra-9-285k-comm-3", "intel-core-ultra-9-285k-comm-5", "intel-core-ultra-9-285k-comm-1", "intel-core-ultra-9-285k-comm-7" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "npu-developer-access", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains no published TOPS figure for an NPU on the desktop 285K itself — the official spec page lists AI frameworks 'Supported by CPU' only (OpenVINO, WindowsML, DirectML, ONNX RT, WebNN), with no NPU TOPS number or dedicated NPU spec line, and generic oneAPI/VTune mentions of 'NPUs from Intel' are not tied to this specific SKU's hardware spec.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-13", "intel-core-ultra-9-285k-docs-11", "intel-core-ultra-9-285k-docs-10" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This story concerns API/UI parity for AI-native software products; a physical CPU has no user-facing UI or API to compare — the axis is a category error for a hardware product.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware CPU product; there is no user data/account to 'export' or platform lock-in to leave — data export/openness is a SaaS/service axis, not applicable to a physical processor.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "openness-open-license", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a physical CPU hardware product, not open-source software; 'reading source under an open license' is a category error for this axis.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is a hardware component, not a hostable software service/application — 'self-hosting the core product' is a category error for this product type.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is local hardware, not a data-hosting/cloud service; data residency/region selection is a SaaS/cloud-storage concept that doesn't apply to a processor product.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "privacy-no-training", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "A CPU is hardware, not a data-processing service or AI model provider; controlling whether user data is used for AI training is a data-governance/privacy-policy axis that applies to cloud/SaaS/AI-service products, not to a silicon component. This axis is a category error for a processor product.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product, not a data-handling or AI service with user data retention policies; data retention/deletion controls are a SaaS/platform axis, not applicable to a processor chip.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a CPU hardware product; telemetry opt-out/usage tracking is a software/service privacy axis that doesn't apply to a processor SKU itself.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "published-spec-sheet", "verdict": "partial", "quality": 6, "confidence": "medium", "rationale": "Intel's ARK specifications page (and the runtime probe) confirms a machine-fetchable spec sheet listing clocks, cache, ECC support, vPro eligibility, and supported AI frameworks (OpenVINO, DirectML, ONNX RT), giving power-users concrete comparable data beyond marketing language. However, the evidence pack lacks explicit AI TOPS figures with stated test conditions, detailed base/turbo power figures, or memory speed/latency specs with test methodology, and much of the docs pack is marketing copy rather than spec data. missing for 10: explicit AI TOPS numbers with test conditions, full power/TDP breakdown, independent verification of spec accuracy.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-13", "intel-core-ultra-9-285k-docs-14", "intel-core-ultra-9-285k-docs-15", "intel-core-ultra-9-285k-probe-rt-1" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "run-70b-local-llm", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "Evidence shows generic 'AI PC' and LLM-tooling marketing (oneDNN/PyTorch optimizations, OpenVINO support) but no published memory bandwidth figures, no addressable-memory/capacity specs, and no benchmarks or claims about running 70B-class quantized models; the CPU is a desktop chip relying on dual-channel DDR5 which is not evidenced as sufficient for practical 70B inference. Missing for 10: memory bandwidth specs, evidence of large-model (70B) local inference support, capacity/quantization guidance, and any hands-on corroboration of local large-LLM performance.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-10", "intel-core-ultra-9-285k-docs-13" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "single-thread-responsiveness", "verdict": "disputed", "quality": 4, "confidence": "medium", "rationale": "Intel markets the 285K on flashy specs and AI/creative workloads, but independent reviews show single-thread/gaming performance actually regressed vs the prior-gen 14900K and lags AMD's 9950X/7800X3D, with Windows-specific single-threaded performance issues reported at launch. missing for 10: independent benchmark data showing leading single-thread performance, resolution of the documented single-thread/gaming regressions, third-party corroboration of 'instant' interactive responsiveness.", "evidenceIds": [ "intel-core-ultra-9-285k-docs-6", "intel-core-ultra-9-285k-comm-2", "intel-core-ultra-9-285k-comm-5", "intel-core-ultra-9-285k-comm-6", "intel-core-ultra-9-285k-comm-4" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "socket-upgrade-path", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains no mention of the CPU's socket (LGA1851) or any stated multi-generation upgrade commitment; specs pages cover cache/clocks/vPro/ECC but not platform longevity. This axis clearly applies to a desktop CPU purchase decision, but no documentation here confirms or denies a multi-gen socket promise.", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "sustained-perf-per-watt", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Independent reviews (Tom's Hardware) confirm the 285K delivers strong productivity/rendering gains with improved power consumption and efficiency versus its 14900K predecessor, and Intel's spec pages document power envelopes (base/turbo power). However, the same reviews note it trails AMD's 9950X in raw perf-per-watt, and no evidence specifically tests sustained long-render/export thermal throttling behavior. Missing for 10: dedicated sustained-load/throttling benchmarks over long export durations, explicit perf-per-watt superiority claims corroborated independently, and creator-specific workload power testing.", "evidenceIds": [ "intel-core-ultra-9-285k-comm-2", "intel-core-ultra-9-285k-comm-3", "intel-core-ultra-9-285k-comm-5", "intel-core-ultra-9-285k-docs-14" ] }, { "productId": "intel-core-ultra-9-285k", "storyId": "thin-quiet-battery", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "intel-core-ultra-9-285k", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack contains no documentation of VT-x/VT-d virtualization extensions, hypervisor compatibility (Hyper-V, KVM, VMware), or container/Docker workflows for the 285K — only general AI/gaming/creator marketing, vPro and ECC specs, and community performance reviews unrelated to virtualization.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-agent-docs", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "Probes show no llms.txt (404), no docs-md, no OpenAPI spec, and the vendor page itself is unreadable to non-browser agents (JS-only shell). This is a hardware chip product, not a docs/API provider, but no agent-oriented documentation infrastructure exists.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-probe-1", "qualcomm-snapdragon-x2-elite-extreme-probe-2", "qualcomm-snapdragon-x2-elite-extreme-probe-3", "qualcomm-snapdragon-x2-elite-extreme-probe-rt-1" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-ai-insights", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a chip/SoC platform, not an end-user application that holds 'my data' and surfaces insights; it only provides underlying NPU compute (TOPS) that OEM software might later use. This is a category error — the axis applies to data-centric software products, not silicon platforms.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-autonomous-automation", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chip platform, not a software/agent product; setting up autonomous background automations is a software application-layer capability outside the scope of a CPU/NPU silicon product's evidence pack.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-builtin-assistant", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a chipset/silicon platform, not a software product with a built-in AI assistant UI; it provides NPU hardware and SDKs for OEMs/developers to build AI features on top, but delegating tasks to an assistant is a wrong-axis question for a chip.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-headless", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-mcp-client", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chipset product (CPU/NPU silicon), not a software agent or platform with an MCP client/server role; plugging MCP servers into it is a category error for a chip.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-mcp-server", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chipset, not an agent/software product that could plug into or serve an MCP server; this axis is a category error for a silicon SoC.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-nl-commands", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-official-cli", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chip/SoC product, not a software tool or platform that would ship an official CLI; the 'AI-native CLI' axis is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-public-api", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-scoped-keys", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware SoC/chip product, not a service or platform issuing API credentials for agents; scoped API credential management is not a fair axis for a CPU/NPU chip.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-sdks", "verdict": "partial", "quality": 5, "confidence": "low", "rationale": "Qualcomm's developer portal explicitly references official SDKs (AI Engine Direct SDK) and Qualcomm AI Hub for deploying models to the Hexagon NPU on Snapdragon X-series chips, giving a genuine AI-native building surface. However, the evidence is a single high-level mention with no code samples, API references, or independent developer corroboration, and probes show no machine-readable docs (llms.txt, openapi) or accessible spec pages without a browser. Missing for 10: detailed SDK documentation/examples, independent developer reports of building against these SDKs, and machine-readable API references.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-6", "qualcomm-snapdragon-x2-elite-extreme-probe-1", "qualcomm-snapdragon-x2-elite-extreme-probe-2" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "agentic-webhooks", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chip product (SoC); webhook event subscriptions are a software/service API concept that does not apply to a physical processor product category.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "api-interactive-docs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chip product (SoC), not an API/SDK service; an interactive API reference with runnable examples is a category error for a physical processor's product page — the axis does not apply.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "api-machine-spec", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware SoC/chip product, not a web service or SaaS platform — there is no product API surface for which an OpenAPI/machine-readable spec would be a meaningful deliverable. The probes confirming no openapi.json exist are consistent with this being a wrong axis for a hardware product rather than a missing capability.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-probe-3" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "api-sandbox", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chip product (CPU/NPU silicon); sandbox testing environments for AI agents are a software/platform concern, not applicable to a chipset's evidence pack.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "api-versioning-policy", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "While Qualcomm offers developer SDKs (AI Engine Direct SDK, AI Hub) that could in principle have API versioning policies, no evidence in the pack shows any versioned API, changelog, or deprecation policy documentation; probes for OpenAPI specs and machine-readable docs all 404.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-6", "qualcomm-snapdragon-x2-elite-extreme-probe-3", "qualcomm-snapdragon-x2-elite-extreme-probe-2" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "automation-bulk-operations", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chipset, not a software/automation tool; 'bulk operations across many items' is a software/workflow capability axis that doesn't apply to a CPU/NPU product itself.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "automation-rules-engine", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware SoC/chip platform, not an automation or workflow-rules product; defining event-triggered automation rules is a software/platform application-layer concern, not something a CPU/NPU chip itself provides.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "automation-scheduled-jobs", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chip (SoC) product, not a software platform or automation tool; scheduling recurring jobs/workflows is a software application capability entirely outside the scope of a chipset's evidence pack.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "automation-versioned-workflows", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chipset, not an automation/workflow platform; versioning, reviewing, and rolling back automations is a category error for this product type.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "developer-toolchain-maturity", "verdict": "partial", "quality": 4, "confidence": "low", "rationale": "Qualcomm's developer portal documents Arm-native Windows toolchains, an AI Engine Direct SDK and AI Hub for the Hexagon NPU, showing some official dev-tooling investment, and one community report praises legacy software compatibility on a prior-gen Snapdragon laptop. But there's no evidence of compiler maturity specifics, no independent corroboration that Windows-on-Arm is treated as a tier-one target by the broader toolchain ecosystem (e.g. major compilers, cross-platform SDKs), and the chip itself hasn't shipped yet (2026 availability). missing for 10: independent evidence of mature/optimized compiler support, third-party tooling parity confirmation, hands-on developer experience reports on the actual X2 Elite hardware.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-6", "qualcomm-snapdragon-x2-elite-extreme-comm-1", "qualcomm-snapdragon-x2-elite-extreme-docs-5" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "expansion-io", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The evidence pack covers CPU cores/clocks, NPU TOPS, and memory bandwidth, but contains no mention whatsoever of PCIe generation/lanes, storage interface specs, or external connectivity (USB/Thunderbolt/display outputs) — the exact I/O headroom details the story asks for. The vendor spec page is even noted to be unreadable by non-browser fetchers, and the recorded 'gap' item only calls out missing TDP/process node/max-memory, not I/O specs at all.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-4", "qualcomm-snapdragon-x2-elite-extreme-probe-rt-1" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "high-fps-gaming", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "No GPU specifications, gaming performance claims, or independent game benchmarks appear anywhere in the evidence pack — the vendor page only covers CPU core count/boost clocks, NPU TOPS, and memory bandwidth, with no mention of integrated GPU class or gaming behavior. The one community comment (about the prior-gen X1 Plus) even suggests gaming is a weak point ('best version of Windows if you don't game'), and the product hasn't shipped yet so no independent game benchmarks exist. Missing for 10: GPU/Adreno specs, vendor gaming performance claims, and any independent game benchmark data.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-comm-1", "qualcomm-snapdragon-x2-elite-extreme-docs-1", "qualcomm-snapdragon-x2-elite-extreme-docs-5" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "local-llm-runtime-support", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Qualcomm's own developer portal documents AI Engine Direct SDK and Qualcomm AI Hub for deploying models to the Hexagon NPU on Snapdragon X-series chips, showing vendor-stack support, but there is no evidence that mainstream runtimes like llama.cpp, MLX, or ONNX Runtime explicitly document support for this specific new silicon (X2 Elite Extreme), and the product hasn't shipped yet (2026). missing for 10: explicit llama.cpp/MLX/ONNX Runtime support statements for X2 Elite Extreme, independent hands-on confirmation of NPU/GPU acceleration, and evidence the AI Hub tooling actually targets this exact chip post-launch.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-6", "qualcomm-snapdragon-x2-elite-extreme-docs-5", "qualcomm-snapdragon-x2-elite-extreme-docs-2" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "media-engine-encode", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "The evidence pack covers CPU cores/clocks, NPU TOPS, and memory bandwidth, but contains no mention of media/video engines, hardware AV1/HEVC encode-decode, or ProRes-class support anywhere in the vendor docs or community commentary. missing for 10: any documented hardware video encode/decode engine specs, codec support list (AV1/HEVC/ProRes), or streaming/editing performance claims.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-1", "qualcomm-snapdragon-x2-elite-extreme-docs-2", "qualcomm-snapdragon-x2-elite-extreme-docs-3", "qualcomm-snapdragon-x2-elite-extreme-docs-4" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "memory-spec-bandwidth", "verdict": "partial", "quality": 5, "confidence": "medium", "rationale": "Vendor publishes memory type (LPDDR5x) and bandwidth (up to 228 GB/s), letting a developer estimate bandwidth-bound workload sizing, but explicitly does not publish a max memory capacity figure, so capacity ceiling must be sourced elsewhere. missing for 10: published max memory capacity, machine-readable spec access (page requires JS rendering, no llms.txt/API).", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-3", "qualcomm-snapdragon-x2-elite-extreme-docs-4", "qualcomm-snapdragon-x2-elite-extreme-probe-rt-1" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "multicore-build-performance", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "Core counts (18-core, 12 Prime + 6 Performance) and boost clocks (up to 5.0GHz Extreme) are documented on Qualcomm's vendor spec page, giving developers concrete compute specs. However, since the chip is unreleased (PCs ship 2026), there are no independent multi-core benchmarks corroborating real-world compiling/parallel-job performance — only unrelated community remarks about the prior-gen X1 Plus and touchpad design. missing for 10: independent multi-core/compile benchmarks, hands-on developer performance reports, TDP/power figures needed to contextualize boost sustainability.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-1", "qualcomm-snapdragon-x2-elite-extreme-docs-5", "qualcomm-snapdragon-x2-elite-extreme-docs-4" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "npu-developer-access", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "Qualcomm publishes an NPU TOPS figure (85 TOPS) and points to an AI Engine Direct SDK / AI Hub for deploying models to the Hexagon NPU, but the precision for the TOPS figure is explicitly not stated, and the X2 Elite Extreme chip itself has not shipped (announced Sept 2025, PCs due 2026), so the 'ships today' condition is unmet for this specific chip. missing for 10: precision spec for the TOPS number, evidence the SDK/runtime targets this specific chip today rather than prior-gen Snapdragon X, and independent developer corroboration of SDK functionality.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-2", "qualcomm-snapdragon-x2-elite-extreme-docs-6", "qualcomm-snapdragon-x2-elite-extreme-docs-5", "qualcomm-snapdragon-x2-elite-extreme-docs-4" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "openness-api-parity", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a physical hardware chip product, not a software/UI application with an API/UI parity concept — the axis is a category error for a CPU/NPU silicon product.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "openness-full-export", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chip (SoC) product, not a data-holding service or application; there is no user data or account to export in open formats. Data export/portability is a category error for a CPU/NPU component.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "openness-open-license", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a proprietary hardware chip product; source-code openness is a category error for a physical silicon SoC, not an applicable axis.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "openness-self-host", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a physical CPU/NPU chip sold to OEMs for laptops, not a hosted service or software product that could be 'self-hosted'; self-hosting is a category error for a silicon product.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "privacy-data-residency", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chip (CPU/NPU) for laptops, not a cloud/data-hosting service; data residency/region storage choice is not an applicable axis for a silicon product.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "privacy-no-training", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chip/SoC, not a service or platform that trains AI models on user data; a data-training opt-out policy is a category error for this product type.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "privacy-retention-controls", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "Snapdragon X2 Elite Extreme is a hardware chipset (CPU/NPU platform), not a data service or application that retains user data; data retention/deletion controls are a software/SaaS privacy axis, not applicable to a silicon product.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "privacy-telemetry-optout", "verdict": "na", "quality": 0, "confidence": "high", "rationale": "This is a hardware chipset product (SoC), not a software/service with telemetry or usage-tracking settings; opt-out of telemetry is a category error for a silicon platform spec.", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "published-spec-sheet", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "Qualcomm publishes some concrete numbers (core counts, boost clocks, NPU TOPS, memory bandwidth) but the story asks for a full transparent spec sheet with test conditions, and the vendor page omits TDP/power envelope, process node, max memory capacity, and doesn't state precision/conditions for the 85 TOPS figure. Missing for 10: TDP/power figures, process node, max memory capacity, stated test conditions/precision for TOPS and clock claims, and independent verification of any of these numbers.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-1", "qualcomm-snapdragon-x2-elite-extreme-docs-2", "qualcomm-snapdragon-x2-elite-extreme-docs-3", "qualcomm-snapdragon-x2-elite-extreme-docs-4" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "run-70b-local-llm", "verdict": "partial", "quality": 4, "confidence": "medium", "rationale": "Qualcomm publishes memory bandwidth (228 GB/s LPDDR5x) and an NPU TOPS figure, and points to an AI Hub/AI Engine Direct SDK for on-device model deployment, but the same spec page explicitly does not publish a max memory capacity figure, which is the critical constraint for whether a 70B-class quantized model can even fit in addressable memory. The product also hasn't shipped yet (2026 laptops), so no hands-on inference benchmarks exist to confirm practicality. Missing for 10: published max RAM capacity/config options, real-world 70B quantized inference benchmarks, independent corroboration of bandwidth/capacity claims.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-3", "qualcomm-snapdragon-x2-elite-extreme-docs-4", "qualcomm-snapdragon-x2-elite-extreme-docs-6", "qualcomm-snapdragon-x2-elite-extreme-docs-5" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "single-thread-responsiveness", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "No independent single-thread benchmarks are present anywhere in the evidence pack; all performance claims are vendor peak-GHz/TOPS figures from a spec page, and the chip hasn't even shipped yet (2026 launch), so third-party validation is impossible at this time. Community comments only cover battery/touchpad, not single-thread performance.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-1", "qualcomm-snapdragon-x2-elite-extreme-docs-5" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "socket-upgrade-path", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "The axis applies to this product kind (peer products hold positive or none verdicts on this story), so lack of evidence for an applicable capability is \"none\", never \"na\". (na/none harmonized at arena bring-up — see pipeline/scripts/na-harmonize.ts.)", "evidenceIds": [] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "sustained-perf-per-watt", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "Qualcomm's own spec page explicitly does not publish a TDP/power envelope (left to OEMs), and the chip hasn't shipped yet (2026), so there is no independent sustained-performance/watt testing available; community evidence is limited to prior-gen (X1) impressions, not this chip.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-4", "qualcomm-snapdragon-x2-elite-extreme-docs-5" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "thin-quiet-battery", "verdict": "none", "quality": 0, "confidence": "medium", "rationale": "No TDP/power envelope is published for the X2 Elite Extreme, no fanless-design OEM commitments are cited, and the chip has not yet shipped in any laptop (PCs due 2026), so there is no battery-life or thermal evidence for this specific product; the only battery-life praise in evidence is about the prior-gen X1 Plus, not this chip.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-4", "qualcomm-snapdragon-x2-elite-extreme-docs-5", "qualcomm-snapdragon-x2-elite-extreme-comm-1" ] }, { "productId": "qualcomm-snapdragon-x2-elite-extreme", "storyId": "virtualization-containers", "verdict": "none", "quality": 0, "confidence": "high", "rationale": "No evidence addresses virtualization support, hypervisor compatibility, or Docker/container workflows on Snapdragon X2 Elite Extreme silicon; developer materials cited only cover Windows-on-Arm native toolchains and NPU SDKs, not VM/container tooling. This is a fair axis for developer silicon, so absence of any supporting evidence yields none, not na.", "evidenceIds": [ "qualcomm-snapdragon-x2-elite-extreme-docs-6", "qualcomm-snapdragon-x2-elite-extreme-docs-4" ] } ]